1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/clock/sifive-fu540-prci.h>
7
8/ {
9	#address-cells = <2>;
10	#size-cells = <2>;
11	compatible = "sifive,fu540-c000", "sifive,fu540";
12
13	aliases {
14		serial0 = &uart0;
15		serial1 = &uart1;
16	};
17
18	chosen {
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24		timebase-frequency = <1000000>;
25		cpu0: cpu@0 {
26			compatible = "sifive,e51", "sifive,rocket0", "riscv";
27			device_type = "cpu";
28			i-cache-block-size = <64>;
29			i-cache-sets = <128>;
30			i-cache-size = <16384>;
31			reg = <0>;
32			riscv,isa = "rv64imac";
33			clocks = <&prci PRCI_CLK_COREPLL>;
34			status = "disabled";
35			cpu0_intc: interrupt-controller {
36				#interrupt-cells = <1>;
37				compatible = "riscv,cpu-intc";
38				interrupt-controller;
39			};
40		};
41		cpu1: cpu@1 {
42			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
43			d-cache-block-size = <64>;
44			d-cache-sets = <64>;
45			d-cache-size = <32768>;
46			d-tlb-sets = <1>;
47			d-tlb-size = <32>;
48			device_type = "cpu";
49			i-cache-block-size = <64>;
50			i-cache-sets = <64>;
51			i-cache-size = <32768>;
52			i-tlb-sets = <1>;
53			i-tlb-size = <32>;
54			mmu-type = "riscv,sv39";
55			reg = <1>;
56			riscv,isa = "rv64imafdc";
57			tlb-split;
58			clocks = <&prci PRCI_CLK_COREPLL>;
59			cpu1_intc: interrupt-controller {
60				#interrupt-cells = <1>;
61				compatible = "riscv,cpu-intc";
62				interrupt-controller;
63			};
64		};
65		cpu2: cpu@2 {
66			clock-frequency = <0>;
67			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
68			d-cache-block-size = <64>;
69			d-cache-sets = <64>;
70			d-cache-size = <32768>;
71			d-tlb-sets = <1>;
72			d-tlb-size = <32>;
73			device_type = "cpu";
74			i-cache-block-size = <64>;
75			i-cache-sets = <64>;
76			i-cache-size = <32768>;
77			i-tlb-sets = <1>;
78			i-tlb-size = <32>;
79			mmu-type = "riscv,sv39";
80			reg = <2>;
81			riscv,isa = "rv64imafdc";
82			tlb-split;
83			clocks = <&prci PRCI_CLK_COREPLL>;
84			cpu2_intc: interrupt-controller {
85				#interrupt-cells = <1>;
86				compatible = "riscv,cpu-intc";
87				interrupt-controller;
88			};
89		};
90		cpu3: cpu@3 {
91			clock-frequency = <0>;
92			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
93			d-cache-block-size = <64>;
94			d-cache-sets = <64>;
95			d-cache-size = <32768>;
96			d-tlb-sets = <1>;
97			d-tlb-size = <32>;
98			device_type = "cpu";
99			i-cache-block-size = <64>;
100			i-cache-sets = <64>;
101			i-cache-size = <32768>;
102			i-tlb-sets = <1>;
103			i-tlb-size = <32>;
104			mmu-type = "riscv,sv39";
105			reg = <3>;
106			riscv,isa = "rv64imafdc";
107			tlb-split;
108			clocks = <&prci PRCI_CLK_COREPLL>;
109			cpu3_intc: interrupt-controller {
110				#interrupt-cells = <1>;
111				compatible = "riscv,cpu-intc";
112				interrupt-controller;
113			};
114		};
115		cpu4: cpu@4 {
116			clock-frequency = <0>;
117			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
118			d-cache-block-size = <64>;
119			d-cache-sets = <64>;
120			d-cache-size = <32768>;
121			d-tlb-sets = <1>;
122			d-tlb-size = <32>;
123			device_type = "cpu";
124			i-cache-block-size = <64>;
125			i-cache-sets = <64>;
126			i-cache-size = <32768>;
127			i-tlb-sets = <1>;
128			i-tlb-size = <32>;
129			mmu-type = "riscv,sv39";
130			reg = <4>;
131			riscv,isa = "rv64imafdc";
132			tlb-split;
133			clocks = <&prci PRCI_CLK_COREPLL>;
134			cpu4_intc: interrupt-controller {
135				#interrupt-cells = <1>;
136				compatible = "riscv,cpu-intc";
137				interrupt-controller;
138			};
139		};
140	};
141	soc {
142		#address-cells = <2>;
143		#size-cells = <2>;
144		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
145		ranges;
146		plic0: interrupt-controller@c000000 {
147			#interrupt-cells = <1>;
148			compatible = "sifive,plic-1.0.0";
149			reg = <0x0 0xc000000 0x0 0x4000000>;
150			riscv,ndev = <53>;
151			interrupt-controller;
152			interrupts-extended = <
153				&cpu0_intc 0xffffffff
154				&cpu1_intc 0xffffffff &cpu1_intc 9
155				&cpu2_intc 0xffffffff &cpu2_intc 9
156				&cpu3_intc 0xffffffff &cpu3_intc 9
157				&cpu4_intc 0xffffffff &cpu4_intc 9>;
158		};
159		prci: clock-controller@10000000 {
160			compatible = "sifive,fu540-c000-prci";
161			reg = <0x0 0x10000000 0x0 0x1000>;
162			clocks = <&hfclk>, <&rtcclk>;
163			#clock-cells = <1>;
164		};
165		uart0: serial@10010000 {
166			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
167			reg = <0x0 0x10010000 0x0 0x1000>;
168			interrupt-parent = <&plic0>;
169			interrupts = <4>;
170			clocks = <&prci PRCI_CLK_TLCLK>;
171			status = "disabled";
172		};
173		uart1: serial@10011000 {
174			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
175			reg = <0x0 0x10011000 0x0 0x1000>;
176			interrupt-parent = <&plic0>;
177			interrupts = <5>;
178			clocks = <&prci PRCI_CLK_TLCLK>;
179			status = "disabled";
180		};
181		i2c0: i2c@10030000 {
182			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
183			reg = <0x0 0x10030000 0x0 0x1000>;
184			interrupt-parent = <&plic0>;
185			interrupts = <50>;
186			clocks = <&prci PRCI_CLK_TLCLK>;
187			reg-shift = <2>;
188			reg-io-width = <1>;
189			#address-cells = <1>;
190			#size-cells = <0>;
191			status = "disabled";
192		};
193		qspi0: spi@10040000 {
194			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
195			reg = <0x0 0x10040000 0x0 0x1000
196			       0x0 0x20000000 0x0 0x10000000>;
197			interrupt-parent = <&plic0>;
198			interrupts = <51>;
199			clocks = <&prci PRCI_CLK_TLCLK>;
200			#address-cells = <1>;
201			#size-cells = <0>;
202			status = "disabled";
203		};
204		qspi1: spi@10041000 {
205			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
206			reg = <0x0 0x10041000 0x0 0x1000
207			       0x0 0x30000000 0x0 0x10000000>;
208			interrupt-parent = <&plic0>;
209			interrupts = <52>;
210			clocks = <&prci PRCI_CLK_TLCLK>;
211			#address-cells = <1>;
212			#size-cells = <0>;
213			status = "disabled";
214		};
215		qspi2: spi@10050000 {
216			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
217			reg = <0x0 0x10050000 0x0 0x1000>;
218			interrupt-parent = <&plic0>;
219			interrupts = <6>;
220			clocks = <&prci PRCI_CLK_TLCLK>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			status = "disabled";
224		};
225		eth0: ethernet@10090000 {
226			compatible = "sifive,fu540-macb";
227			interrupt-parent = <&plic0>;
228			interrupts = <53>;
229			reg = <0x0 0x10090000 0x0 0x2000
230			       0x0 0x100a0000 0x0 0x1000>;
231			reg-names = "control";
232			status = "disabled";
233			local-mac-address = [00 00 00 00 00 00];
234			clock-names = "pclk", "hclk";
235			clocks = <&prci PRCI_CLK_GEMGXLPLL>,
236				 <&prci PRCI_CLK_GEMGXLPLL>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239		};
240
241	};
242};
243