1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
4 *
5 * Copyright (c) 2012-2017 Mentor Graphics Inc.
6 */
7 #include <linux/clk.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/platform_device.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-mc.h>
18 #include <media/v4l2-subdev.h>
19 #include "imx-media.h"
20
21 /*
22 * there must be 5 pads: 1 input pad from sensor, and
23 * the 4 virtual channel output pads
24 */
25 #define CSI2_SINK_PAD 0
26 #define CSI2_NUM_SINK_PADS 1
27 #define CSI2_NUM_SRC_PADS 4
28 #define CSI2_NUM_PADS 5
29
30 /*
31 * The default maximum bit-rate per lane in Mbps, if the
32 * source subdev does not provide V4L2_CID_LINK_FREQ.
33 */
34 #define CSI2_DEFAULT_MAX_MBPS 849
35
36 struct csi2_dev {
37 struct device *dev;
38 struct v4l2_subdev sd;
39 struct v4l2_async_notifier notifier;
40 struct media_pad pad[CSI2_NUM_PADS];
41 struct clk *dphy_clk;
42 struct clk *pllref_clk;
43 struct clk *pix_clk; /* what is this? */
44 void __iomem *base;
45
46 struct v4l2_subdev *remote;
47 unsigned int remote_pad;
48 unsigned short data_lanes;
49
50 /* lock to protect all members below */
51 struct mutex lock;
52
53 struct v4l2_mbus_framefmt format_mbus;
54
55 int stream_count;
56 struct v4l2_subdev *src_sd;
57 bool sink_linked[CSI2_NUM_SRC_PADS];
58 };
59
60 #define DEVICE_NAME "imx6-mipi-csi2"
61
62 /* Register offsets */
63 #define CSI2_VERSION 0x000
64 #define CSI2_N_LANES 0x004
65 #define CSI2_PHY_SHUTDOWNZ 0x008
66 #define CSI2_DPHY_RSTZ 0x00c
67 #define CSI2_RESETN 0x010
68 #define CSI2_PHY_STATE 0x014
69 #define PHY_STOPSTATEDATA_BIT 4
70 #define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n))
71 #define PHY_RXCLKACTIVEHS BIT(8)
72 #define PHY_RXULPSCLKNOT BIT(9)
73 #define PHY_STOPSTATECLK BIT(10)
74 #define CSI2_DATA_IDS_1 0x018
75 #define CSI2_DATA_IDS_2 0x01c
76 #define CSI2_ERR1 0x020
77 #define CSI2_ERR2 0x024
78 #define CSI2_MSK1 0x028
79 #define CSI2_MSK2 0x02c
80 #define CSI2_PHY_TST_CTRL0 0x030
81 #define PHY_TESTCLR BIT(0)
82 #define PHY_TESTCLK BIT(1)
83 #define CSI2_PHY_TST_CTRL1 0x034
84 #define PHY_TESTEN BIT(16)
85 /*
86 * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
87 * not part of the MIPI CSI-2 core, but its registers fall in the
88 * same register map range.
89 */
90 #define CSI2IPU_GASKET 0xf00
91 #define CSI2IPU_YUV422_YUYV BIT(2)
92
sd_to_dev(struct v4l2_subdev * sdev)93 static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev)
94 {
95 return container_of(sdev, struct csi2_dev, sd);
96 }
97
notifier_to_dev(struct v4l2_async_notifier * n)98 static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n)
99 {
100 return container_of(n, struct csi2_dev, notifier);
101 }
102
103 /*
104 * The required sequence of MIPI CSI-2 startup as specified in the i.MX6
105 * reference manual is as follows:
106 *
107 * 1. Deassert presetn signal (global reset).
108 * It's not clear what this "global reset" signal is (maybe APB
109 * global reset), but in any case this step would be probably
110 * be carried out during driver load in csi2_probe().
111 *
112 * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
113 * This must be carried out by the MIPI sensor's s_power(ON) subdev
114 * op.
115 *
116 * 3. D-PHY initialization.
117 * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
118 * deassert PHY_RSTZ, deassert CSI2_RESETN).
119 * 5. Read the PHY status register (PHY_STATE) to confirm that all data and
120 * clock lanes of the D-PHY are in LP-11 state.
121 * 6. Configure the MIPI Camera Sensor to start transmitting a clock on the
122 * D-PHY clock lane.
123 * 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE)
124 * to confirm that the D-PHY is receiving a clock on the D-PHY clock lane.
125 *
126 * All steps 3 through 7 are carried out by csi2_s_stream(ON) here. Step
127 * 6 is accomplished by calling the source subdev's s_stream(ON) between
128 * steps 5 and 7.
129 */
130
csi2_enable(struct csi2_dev * csi2,bool enable)131 static void csi2_enable(struct csi2_dev *csi2, bool enable)
132 {
133 if (enable) {
134 writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ);
135 writel(0x1, csi2->base + CSI2_DPHY_RSTZ);
136 writel(0x1, csi2->base + CSI2_RESETN);
137 } else {
138 writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ);
139 writel(0x0, csi2->base + CSI2_DPHY_RSTZ);
140 writel(0x0, csi2->base + CSI2_RESETN);
141 }
142 }
143
csi2_set_lanes(struct csi2_dev * csi2,unsigned int lanes)144 static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes)
145 {
146 writel(lanes - 1, csi2->base + CSI2_N_LANES);
147 }
148
dw_mipi_csi2_phy_write(struct csi2_dev * csi2,u32 test_code,u32 test_data)149 static void dw_mipi_csi2_phy_write(struct csi2_dev *csi2,
150 u32 test_code, u32 test_data)
151 {
152 /* Clear PHY test interface */
153 writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0);
154 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1);
155 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
156
157 /* Raise test interface strobe signal */
158 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
159
160 /* Configure address write on falling edge and lower strobe signal */
161 writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1);
162 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
163
164 /* Configure data write on rising edge and raise strobe signal */
165 writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1);
166 writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
167
168 /* Clear strobe signal */
169 writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
170 }
171
172 /*
173 * This table is based on the table documented at
174 * https://community.nxp.com/docs/DOC-94312. It assumes
175 * a 27MHz D-PHY pll reference clock.
176 */
177 static const struct {
178 u32 max_mbps;
179 u32 hsfreqrange_sel;
180 } hsfreq_map[] = {
181 { 90, 0x00}, {100, 0x20}, {110, 0x40}, {125, 0x02},
182 {140, 0x22}, {150, 0x42}, {160, 0x04}, {180, 0x24},
183 {200, 0x44}, {210, 0x06}, {240, 0x26}, {250, 0x46},
184 {270, 0x08}, {300, 0x28}, {330, 0x48}, {360, 0x2a},
185 {400, 0x4a}, {450, 0x0c}, {500, 0x2c}, {550, 0x0e},
186 {600, 0x2e}, {650, 0x10}, {700, 0x30}, {750, 0x12},
187 {800, 0x32}, {850, 0x14}, {900, 0x34}, {950, 0x54},
188 {1000, 0x74},
189 };
190
max_mbps_to_hsfreqrange_sel(u32 max_mbps)191 static int max_mbps_to_hsfreqrange_sel(u32 max_mbps)
192 {
193 int i;
194
195 for (i = 0; i < ARRAY_SIZE(hsfreq_map); i++)
196 if (hsfreq_map[i].max_mbps > max_mbps)
197 return hsfreq_map[i].hsfreqrange_sel;
198
199 return -EINVAL;
200 }
201
csi2_dphy_init(struct csi2_dev * csi2)202 static int csi2_dphy_init(struct csi2_dev *csi2)
203 {
204 struct v4l2_ctrl *ctrl;
205 u32 mbps_per_lane;
206 int sel;
207
208 ctrl = v4l2_ctrl_find(csi2->src_sd->ctrl_handler,
209 V4L2_CID_LINK_FREQ);
210 if (!ctrl)
211 mbps_per_lane = CSI2_DEFAULT_MAX_MBPS;
212 else
213 mbps_per_lane = DIV_ROUND_UP_ULL(2 * ctrl->qmenu_int[ctrl->val],
214 USEC_PER_SEC);
215
216 sel = max_mbps_to_hsfreqrange_sel(mbps_per_lane);
217 if (sel < 0)
218 return sel;
219
220 dw_mipi_csi2_phy_write(csi2, 0x44, sel);
221
222 return 0;
223 }
224
225 /*
226 * Waits for ultra-low-power state on D-PHY clock lane. This is currently
227 * unused and may not be needed at all, but keep around just in case.
228 */
csi2_dphy_wait_ulp(struct csi2_dev * csi2)229 static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2)
230 {
231 u32 reg;
232 int ret;
233
234 /* wait for ULP on clock lane */
235 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
236 !(reg & PHY_RXULPSCLKNOT), 0, 500000);
237 if (ret) {
238 v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg);
239 return ret;
240 }
241
242 /* wait until no errors on bus */
243 ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg,
244 reg == 0x0, 0, 500000);
245 if (ret) {
246 v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg);
247 return ret;
248 }
249
250 return 0;
251 }
252
253 /* Waits for low-power LP-11 state on data and clock lanes. */
csi2_dphy_wait_stopstate(struct csi2_dev * csi2,unsigned int lanes)254 static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes)
255 {
256 u32 mask, reg;
257 int ret;
258
259 mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT);
260
261 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
262 (reg & mask) == mask, 0, 500000);
263 if (ret) {
264 v4l2_warn(&csi2->sd, "LP-11 wait timeout, likely a sensor driver bug, expect capture failures.\n");
265 v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg);
266 }
267 }
268
269 /* Wait for active clock on the clock lane. */
csi2_dphy_wait_clock_lane(struct csi2_dev * csi2)270 static int csi2_dphy_wait_clock_lane(struct csi2_dev *csi2)
271 {
272 u32 reg;
273 int ret;
274
275 ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg,
276 (reg & PHY_RXCLKACTIVEHS), 0, 500000);
277 if (ret) {
278 v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",
279 reg);
280 return ret;
281 }
282
283 return 0;
284 }
285
286 /* Setup the i.MX CSI2IPU Gasket */
csi2ipu_gasket_init(struct csi2_dev * csi2)287 static void csi2ipu_gasket_init(struct csi2_dev *csi2)
288 {
289 u32 reg = 0;
290
291 switch (csi2->format_mbus.code) {
292 case MEDIA_BUS_FMT_YUYV8_2X8:
293 case MEDIA_BUS_FMT_YUYV8_1X16:
294 reg = CSI2IPU_YUV422_YUYV;
295 break;
296 default:
297 break;
298 }
299
300 writel(reg, csi2->base + CSI2IPU_GASKET);
301 }
302
csi2_get_active_lanes(struct csi2_dev * csi2,unsigned int * lanes)303 static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes)
304 {
305 struct v4l2_mbus_config mbus_config = { 0 };
306 int ret;
307
308 *lanes = csi2->data_lanes;
309
310 ret = v4l2_subdev_call(csi2->remote, pad, get_mbus_config,
311 csi2->remote_pad, &mbus_config);
312 if (ret == -ENOIOCTLCMD) {
313 dev_dbg(csi2->dev, "No remote mbus configuration available\n");
314 return 0;
315 }
316
317 if (ret) {
318 dev_err(csi2->dev, "Failed to get remote mbus configuration\n");
319 return ret;
320 }
321
322 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
323 dev_err(csi2->dev, "Unsupported media bus type %u\n",
324 mbus_config.type);
325 return -EINVAL;
326 }
327
328 if (mbus_config.bus.mipi_csi2.num_data_lanes > csi2->data_lanes) {
329 dev_err(csi2->dev,
330 "Unsupported mbus config: too many data lanes %u\n",
331 mbus_config.bus.mipi_csi2.num_data_lanes);
332 return -EINVAL;
333 }
334
335 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes;
336
337 return 0;
338 }
339
csi2_start(struct csi2_dev * csi2)340 static int csi2_start(struct csi2_dev *csi2)
341 {
342 unsigned int lanes;
343 int ret;
344
345 ret = clk_prepare_enable(csi2->pix_clk);
346 if (ret)
347 return ret;
348
349 /* setup the gasket */
350 csi2ipu_gasket_init(csi2);
351
352 /* Step 3 */
353 ret = csi2_dphy_init(csi2);
354 if (ret)
355 goto err_disable_clk;
356
357 ret = csi2_get_active_lanes(csi2, &lanes);
358 if (ret)
359 goto err_disable_clk;
360
361 /* Step 4 */
362 csi2_set_lanes(csi2, lanes);
363 csi2_enable(csi2, true);
364
365 /* Step 5 */
366 ret = v4l2_subdev_call(csi2->src_sd, video, pre_streamon,
367 V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP);
368 if (ret && ret != -ENOIOCTLCMD)
369 goto err_assert_reset;
370 csi2_dphy_wait_stopstate(csi2, lanes);
371
372 /* Step 6 */
373 ret = v4l2_subdev_call(csi2->src_sd, video, s_stream, 1);
374 ret = (ret && ret != -ENOIOCTLCMD) ? ret : 0;
375 if (ret)
376 goto err_stop_lp11;
377
378 /* Step 7 */
379 ret = csi2_dphy_wait_clock_lane(csi2);
380 if (ret)
381 goto err_stop_upstream;
382
383 return 0;
384
385 err_stop_upstream:
386 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
387 err_stop_lp11:
388 v4l2_subdev_call(csi2->src_sd, video, post_streamoff);
389 err_assert_reset:
390 csi2_enable(csi2, false);
391 err_disable_clk:
392 clk_disable_unprepare(csi2->pix_clk);
393 return ret;
394 }
395
csi2_stop(struct csi2_dev * csi2)396 static void csi2_stop(struct csi2_dev *csi2)
397 {
398 /* stop upstream */
399 v4l2_subdev_call(csi2->src_sd, video, s_stream, 0);
400 v4l2_subdev_call(csi2->src_sd, video, post_streamoff);
401
402 csi2_enable(csi2, false);
403 clk_disable_unprepare(csi2->pix_clk);
404 }
405
406 /*
407 * V4L2 subdev operations.
408 */
409
csi2_s_stream(struct v4l2_subdev * sd,int enable)410 static int csi2_s_stream(struct v4l2_subdev *sd, int enable)
411 {
412 struct csi2_dev *csi2 = sd_to_dev(sd);
413 int i, ret = 0;
414
415 mutex_lock(&csi2->lock);
416
417 if (!csi2->src_sd) {
418 ret = -EPIPE;
419 goto out;
420 }
421
422 for (i = 0; i < CSI2_NUM_SRC_PADS; i++) {
423 if (csi2->sink_linked[i])
424 break;
425 }
426 if (i >= CSI2_NUM_SRC_PADS) {
427 ret = -EPIPE;
428 goto out;
429 }
430
431 /*
432 * enable/disable streaming only if stream_count is
433 * going from 0 to 1 / 1 to 0.
434 */
435 if (csi2->stream_count != !enable)
436 goto update_count;
437
438 dev_dbg(csi2->dev, "stream %s\n", enable ? "ON" : "OFF");
439 if (enable)
440 ret = csi2_start(csi2);
441 else
442 csi2_stop(csi2);
443 if (ret)
444 goto out;
445
446 update_count:
447 csi2->stream_count += enable ? 1 : -1;
448 if (csi2->stream_count < 0)
449 csi2->stream_count = 0;
450 out:
451 mutex_unlock(&csi2->lock);
452 return ret;
453 }
454
csi2_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)455 static int csi2_link_setup(struct media_entity *entity,
456 const struct media_pad *local,
457 const struct media_pad *remote, u32 flags)
458 {
459 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
460 struct csi2_dev *csi2 = sd_to_dev(sd);
461 struct v4l2_subdev *remote_sd;
462 int ret = 0;
463
464 dev_dbg(csi2->dev, "link setup %s -> %s", remote->entity->name,
465 local->entity->name);
466
467 remote_sd = media_entity_to_v4l2_subdev(remote->entity);
468
469 mutex_lock(&csi2->lock);
470
471 if (local->flags & MEDIA_PAD_FL_SOURCE) {
472 if (flags & MEDIA_LNK_FL_ENABLED) {
473 if (csi2->sink_linked[local->index - 1]) {
474 ret = -EBUSY;
475 goto out;
476 }
477 csi2->sink_linked[local->index - 1] = true;
478 } else {
479 csi2->sink_linked[local->index - 1] = false;
480 }
481 } else {
482 if (flags & MEDIA_LNK_FL_ENABLED) {
483 if (csi2->src_sd) {
484 ret = -EBUSY;
485 goto out;
486 }
487 csi2->src_sd = remote_sd;
488 } else {
489 csi2->src_sd = NULL;
490 }
491 }
492
493 out:
494 mutex_unlock(&csi2->lock);
495 return ret;
496 }
497
498 static struct v4l2_mbus_framefmt *
__csi2_get_fmt(struct csi2_dev * csi2,struct v4l2_subdev_state * sd_state,unsigned int pad,enum v4l2_subdev_format_whence which)499 __csi2_get_fmt(struct csi2_dev *csi2, struct v4l2_subdev_state *sd_state,
500 unsigned int pad, enum v4l2_subdev_format_whence which)
501 {
502 if (which == V4L2_SUBDEV_FORMAT_TRY)
503 return v4l2_subdev_get_try_format(&csi2->sd, sd_state, pad);
504 else
505 return &csi2->format_mbus;
506 }
507
csi2_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * sdformat)508 static int csi2_get_fmt(struct v4l2_subdev *sd,
509 struct v4l2_subdev_state *sd_state,
510 struct v4l2_subdev_format *sdformat)
511 {
512 struct csi2_dev *csi2 = sd_to_dev(sd);
513 struct v4l2_mbus_framefmt *fmt;
514
515 mutex_lock(&csi2->lock);
516
517 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
518
519 sdformat->format = *fmt;
520
521 mutex_unlock(&csi2->lock);
522
523 return 0;
524 }
525
csi2_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * sdformat)526 static int csi2_set_fmt(struct v4l2_subdev *sd,
527 struct v4l2_subdev_state *sd_state,
528 struct v4l2_subdev_format *sdformat)
529 {
530 struct csi2_dev *csi2 = sd_to_dev(sd);
531 struct v4l2_mbus_framefmt *fmt;
532 int ret = 0;
533
534 if (sdformat->pad >= CSI2_NUM_PADS)
535 return -EINVAL;
536
537 mutex_lock(&csi2->lock);
538
539 if (csi2->stream_count > 0) {
540 ret = -EBUSY;
541 goto out;
542 }
543
544 /* Output pads mirror active input pad, no limits on input pads */
545 if (sdformat->pad != CSI2_SINK_PAD)
546 sdformat->format = csi2->format_mbus;
547
548 fmt = __csi2_get_fmt(csi2, sd_state, sdformat->pad, sdformat->which);
549
550 *fmt = sdformat->format;
551 out:
552 mutex_unlock(&csi2->lock);
553 return ret;
554 }
555
csi2_registered(struct v4l2_subdev * sd)556 static int csi2_registered(struct v4l2_subdev *sd)
557 {
558 struct csi2_dev *csi2 = sd_to_dev(sd);
559
560 /* set a default mbus format */
561 return imx_media_init_mbus_fmt(&csi2->format_mbus,
562 IMX_MEDIA_DEF_PIX_WIDTH,
563 IMX_MEDIA_DEF_PIX_HEIGHT, 0,
564 V4L2_FIELD_NONE, NULL);
565 }
566
567 static const struct media_entity_operations csi2_entity_ops = {
568 .link_setup = csi2_link_setup,
569 .link_validate = v4l2_subdev_link_validate,
570 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
571 };
572
573 static const struct v4l2_subdev_video_ops csi2_video_ops = {
574 .s_stream = csi2_s_stream,
575 };
576
577 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
578 .init_cfg = imx_media_init_cfg,
579 .get_fmt = csi2_get_fmt,
580 .set_fmt = csi2_set_fmt,
581 };
582
583 static const struct v4l2_subdev_ops csi2_subdev_ops = {
584 .video = &csi2_video_ops,
585 .pad = &csi2_pad_ops,
586 };
587
588 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
589 .registered = csi2_registered,
590 };
591
csi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)592 static int csi2_notify_bound(struct v4l2_async_notifier *notifier,
593 struct v4l2_subdev *sd,
594 struct v4l2_async_subdev *asd)
595 {
596 struct csi2_dev *csi2 = notifier_to_dev(notifier);
597 struct media_pad *sink = &csi2->sd.entity.pads[CSI2_SINK_PAD];
598 int pad;
599
600 pad = media_entity_get_fwnode_pad(&sd->entity, asd->match.fwnode,
601 MEDIA_PAD_FL_SOURCE);
602 if (pad < 0) {
603 dev_err(csi2->dev, "Failed to find pad for %s\n", sd->name);
604 return pad;
605 }
606
607 csi2->remote = sd;
608 csi2->remote_pad = pad;
609
610 dev_dbg(csi2->dev, "Bound %s pad: %d\n", sd->name, pad);
611
612 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
613 }
614
csi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)615 static void csi2_notify_unbind(struct v4l2_async_notifier *notifier,
616 struct v4l2_subdev *sd,
617 struct v4l2_async_subdev *asd)
618 {
619 struct csi2_dev *csi2 = notifier_to_dev(notifier);
620
621 csi2->remote = NULL;
622 }
623
624 static const struct v4l2_async_notifier_operations csi2_notify_ops = {
625 .bound = csi2_notify_bound,
626 .unbind = csi2_notify_unbind,
627 };
628
csi2_async_register(struct csi2_dev * csi2)629 static int csi2_async_register(struct csi2_dev *csi2)
630 {
631 struct v4l2_fwnode_endpoint vep = {
632 .bus_type = V4L2_MBUS_CSI2_DPHY,
633 };
634 struct v4l2_async_subdev *asd;
635 struct fwnode_handle *ep;
636 int ret;
637
638 v4l2_async_nf_init(&csi2->notifier);
639
640 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0,
641 FWNODE_GRAPH_ENDPOINT_NEXT);
642 if (!ep)
643 return -ENOTCONN;
644
645 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
646 if (ret)
647 goto err_parse;
648
649 csi2->data_lanes = vep.bus.mipi_csi2.num_data_lanes;
650
651 dev_dbg(csi2->dev, "data lanes: %d\n", vep.bus.mipi_csi2.num_data_lanes);
652 dev_dbg(csi2->dev, "flags: 0x%08x\n", vep.bus.mipi_csi2.flags);
653
654 asd = v4l2_async_nf_add_fwnode_remote(&csi2->notifier, ep,
655 struct v4l2_async_subdev);
656 fwnode_handle_put(ep);
657
658 if (IS_ERR(asd))
659 return PTR_ERR(asd);
660
661 csi2->notifier.ops = &csi2_notify_ops;
662
663 ret = v4l2_async_subdev_nf_register(&csi2->sd, &csi2->notifier);
664 if (ret)
665 return ret;
666
667 return v4l2_async_register_subdev(&csi2->sd);
668
669 err_parse:
670 fwnode_handle_put(ep);
671 return ret;
672 }
673
csi2_probe(struct platform_device * pdev)674 static int csi2_probe(struct platform_device *pdev)
675 {
676 struct csi2_dev *csi2;
677 struct resource *res;
678 int i, ret;
679
680 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
681 if (!csi2)
682 return -ENOMEM;
683
684 csi2->dev = &pdev->dev;
685
686 v4l2_subdev_init(&csi2->sd, &csi2_subdev_ops);
687 v4l2_set_subdevdata(&csi2->sd, &pdev->dev);
688 csi2->sd.internal_ops = &csi2_internal_ops;
689 csi2->sd.entity.ops = &csi2_entity_ops;
690 csi2->sd.dev = &pdev->dev;
691 csi2->sd.owner = THIS_MODULE;
692 csi2->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
693 strscpy(csi2->sd.name, DEVICE_NAME, sizeof(csi2->sd.name));
694 csi2->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
695 csi2->sd.grp_id = IMX_MEDIA_GRP_ID_CSI2;
696
697 for (i = 0; i < CSI2_NUM_PADS; i++) {
698 csi2->pad[i].flags = (i == CSI2_SINK_PAD) ?
699 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
700 }
701
702 ret = media_entity_pads_init(&csi2->sd.entity, CSI2_NUM_PADS,
703 csi2->pad);
704 if (ret)
705 return ret;
706
707 csi2->pllref_clk = devm_clk_get(&pdev->dev, "ref");
708 if (IS_ERR(csi2->pllref_clk)) {
709 v4l2_err(&csi2->sd, "failed to get pll reference clock\n");
710 return PTR_ERR(csi2->pllref_clk);
711 }
712
713 csi2->dphy_clk = devm_clk_get(&pdev->dev, "dphy");
714 if (IS_ERR(csi2->dphy_clk)) {
715 v4l2_err(&csi2->sd, "failed to get dphy clock\n");
716 return PTR_ERR(csi2->dphy_clk);
717 }
718
719 csi2->pix_clk = devm_clk_get(&pdev->dev, "pix");
720 if (IS_ERR(csi2->pix_clk)) {
721 v4l2_err(&csi2->sd, "failed to get pixel clock\n");
722 return PTR_ERR(csi2->pix_clk);
723 }
724
725 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
726 if (!res) {
727 v4l2_err(&csi2->sd, "failed to get platform resources\n");
728 return -ENODEV;
729 }
730
731 csi2->base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
732 if (!csi2->base)
733 return -ENOMEM;
734
735 mutex_init(&csi2->lock);
736
737 ret = clk_prepare_enable(csi2->pllref_clk);
738 if (ret) {
739 v4l2_err(&csi2->sd, "failed to enable pllref_clk\n");
740 goto rmmutex;
741 }
742
743 ret = clk_prepare_enable(csi2->dphy_clk);
744 if (ret) {
745 v4l2_err(&csi2->sd, "failed to enable dphy_clk\n");
746 goto pllref_off;
747 }
748
749 platform_set_drvdata(pdev, &csi2->sd);
750
751 ret = csi2_async_register(csi2);
752 if (ret)
753 goto clean_notifier;
754
755 return 0;
756
757 clean_notifier:
758 v4l2_async_nf_unregister(&csi2->notifier);
759 v4l2_async_nf_cleanup(&csi2->notifier);
760 clk_disable_unprepare(csi2->dphy_clk);
761 pllref_off:
762 clk_disable_unprepare(csi2->pllref_clk);
763 rmmutex:
764 mutex_destroy(&csi2->lock);
765 return ret;
766 }
767
csi2_remove(struct platform_device * pdev)768 static int csi2_remove(struct platform_device *pdev)
769 {
770 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
771 struct csi2_dev *csi2 = sd_to_dev(sd);
772
773 v4l2_async_nf_unregister(&csi2->notifier);
774 v4l2_async_nf_cleanup(&csi2->notifier);
775 v4l2_async_unregister_subdev(sd);
776 clk_disable_unprepare(csi2->dphy_clk);
777 clk_disable_unprepare(csi2->pllref_clk);
778 mutex_destroy(&csi2->lock);
779 media_entity_cleanup(&sd->entity);
780
781 return 0;
782 }
783
784 static const struct of_device_id csi2_dt_ids[] = {
785 { .compatible = "fsl,imx6-mipi-csi2", },
786 { /* sentinel */ }
787 };
788 MODULE_DEVICE_TABLE(of, csi2_dt_ids);
789
790 static struct platform_driver csi2_driver = {
791 .driver = {
792 .name = DEVICE_NAME,
793 .of_match_table = csi2_dt_ids,
794 },
795 .probe = csi2_probe,
796 .remove = csi2_remove,
797 };
798
799 module_platform_driver(csi2_driver);
800
801 MODULE_DESCRIPTION("i.MX5/6 MIPI CSI-2 Receiver driver");
802 MODULE_AUTHOR("Steve Longerbeam <steve_longerbeam@mentor.com>");
803 MODULE_LICENSE("GPL");
804