1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <linux/of_address.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_domain.h>
10 #include <linux/bitfield.h>
11 #include <linux/regmap.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/reset-controller.h>
15 #include <linux/reset.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <dt-bindings/power/meson8-power.h>
19 #include <dt-bindings/power/meson-axg-power.h>
20 #include <dt-bindings/power/meson-g12a-power.h>
21 #include <dt-bindings/power/meson-gxbb-power.h>
22 #include <dt-bindings/power/meson-sm1-power.h>
23
24 /* AO Offsets */
25
26 #define GX_AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
27 #define GX_AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
28
29 /*
30 * Meson8/Meson8b/Meson8m2 only expose the power management registers of the
31 * AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03
32 * and so on.
33 */
34 #define MESON8_AO_RTI_GEN_PWR_SLEEP0 (0x02 << 2)
35 #define MESON8_AO_RTI_GEN_PWR_ISO0 (0x03 << 2)
36
37 /* HHI Offsets */
38
39 #define HHI_MEM_PD_REG0 (0x40 << 2)
40 #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
41 #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
42 #define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
43 #define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
44 #define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
45 #define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
46 #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
47 #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
48
49 #define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
50 #define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
51
52 struct meson_ee_pwrc;
53 struct meson_ee_pwrc_domain;
54
55 struct meson_ee_pwrc_mem_domain {
56 unsigned int reg;
57 unsigned int mask;
58 };
59
60 struct meson_ee_pwrc_top_domain {
61 unsigned int sleep_reg;
62 unsigned int sleep_mask;
63 unsigned int iso_reg;
64 unsigned int iso_mask;
65 };
66
67 struct meson_ee_pwrc_domain_desc {
68 char *name;
69 unsigned int reset_names_count;
70 unsigned int clk_names_count;
71 struct meson_ee_pwrc_top_domain *top_pd;
72 unsigned int mem_pd_count;
73 struct meson_ee_pwrc_mem_domain *mem_pd;
74 bool (*is_powered_off)(struct meson_ee_pwrc_domain *pwrc_domain);
75 };
76
77 struct meson_ee_pwrc_domain_data {
78 unsigned int count;
79 struct meson_ee_pwrc_domain_desc *domains;
80 };
81
82 /* TOP Power Domains */
83
84 static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
85 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
86 .sleep_mask = BIT(8),
87 .iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
88 .iso_mask = BIT(9),
89 };
90
91 static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
92 .sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
93 .sleep_mask = BIT(8),
94 .iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
95 .iso_mask = BIT(9),
96 };
97
98 #define SM1_EE_PD(__bit) \
99 { \
100 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
101 .sleep_mask = BIT(__bit), \
102 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
103 .iso_mask = BIT(__bit), \
104 }
105
106 static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
107 static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
108 static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
109 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
110 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
111
112 static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {
113 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
114 .sleep_mask = BIT(16) | BIT(17),
115 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0,
116 .iso_mask = BIT(16) | BIT(17),
117 };
118
119 /* Memory PD Domains */
120
121 #define VPU_MEMPD(__reg) \
122 { __reg, GENMASK(1, 0) }, \
123 { __reg, GENMASK(3, 2) }, \
124 { __reg, GENMASK(5, 4) }, \
125 { __reg, GENMASK(7, 6) }, \
126 { __reg, GENMASK(9, 8) }, \
127 { __reg, GENMASK(11, 10) }, \
128 { __reg, GENMASK(13, 12) }, \
129 { __reg, GENMASK(15, 14) }, \
130 { __reg, GENMASK(17, 16) }, \
131 { __reg, GENMASK(19, 18) }, \
132 { __reg, GENMASK(21, 20) }, \
133 { __reg, GENMASK(23, 22) }, \
134 { __reg, GENMASK(25, 24) }, \
135 { __reg, GENMASK(27, 26) }, \
136 { __reg, GENMASK(29, 28) }, \
137 { __reg, GENMASK(31, 30) }
138
139 #define VPU_HHI_MEMPD(__reg) \
140 { __reg, BIT(8) }, \
141 { __reg, BIT(9) }, \
142 { __reg, BIT(10) }, \
143 { __reg, BIT(11) }, \
144 { __reg, BIT(12) }, \
145 { __reg, BIT(13) }, \
146 { __reg, BIT(14) }, \
147 { __reg, BIT(15) }
148
149 static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = {
150 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
151 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
152 };
153
154 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
155 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
156 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
157 VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
158 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
159 };
160
161 static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
162 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
163 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
164 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
165 };
166
167 static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = {
168 { HHI_MEM_PD_REG0, GENMASK(3, 2) },
169 };
170
171 static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = {
172 { HHI_MEM_PD_REG0, GENMASK(1, 0) },
173 };
174
175 static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = {
176 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
177 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
178 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
179 };
180
181 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
182 VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
183 VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
184 VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
185 VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
186 { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
187 { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
188 { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
189 { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
190 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
191 };
192
193 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
194 { HHI_NANOQ_MEM_PD_REG0, 0xff },
195 { HHI_NANOQ_MEM_PD_REG1, 0xff },
196 };
197
198 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
199 { HHI_MEM_PD_REG0, GENMASK(31, 30) },
200 };
201
202 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
203 { HHI_MEM_PD_REG0, GENMASK(29, 26) },
204 };
205
206 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
207 { HHI_MEM_PD_REG0, GENMASK(25, 18) },
208 };
209
210 static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = {
211 { HHI_MEM_PD_REG0, GENMASK(5, 4) },
212 };
213
214 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
215 { HHI_MEM_PD_REG0, GENMASK(5, 4) },
216 { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
217 { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
218 { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
219 { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
220 { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
221 { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
222 { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
223 { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
224 { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
225 { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
226 { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
227 { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
228 };
229
230 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
231 { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
232 { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
233 };
234
235 #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
236 { \
237 .name = __name, \
238 .reset_names_count = __resets, \
239 .clk_names_count = __clks, \
240 .top_pd = __top_pd, \
241 .mem_pd_count = ARRAY_SIZE(__mem), \
242 .mem_pd = __mem, \
243 .is_powered_off = __is_pwr_off, \
244 }
245
246 #define TOP_PD(__name, __top_pd, __mem, __is_pwr_off) \
247 { \
248 .name = __name, \
249 .top_pd = __top_pd, \
250 .mem_pd_count = ARRAY_SIZE(__mem), \
251 .mem_pd = __mem, \
252 .is_powered_off = __is_pwr_off, \
253 }
254
255 #define MEM_PD(__name, __mem) \
256 TOP_PD(__name, NULL, __mem, NULL)
257
258 static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain);
259
260 static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = {
261 [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu,
262 pwrc_ee_is_powered_off, 5, 2),
263 [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
264 [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio),
265 };
266
267 static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
268 [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
269 pwrc_ee_is_powered_off, 11, 2),
270 [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
271 [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
272 pwrc_ee_is_powered_off),
273 };
274
275 static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
276 [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
277 pwrc_ee_is_powered_off, 12, 2),
278 [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
279 };
280
281 static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = {
282 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
283 meson8_pwrc_mem_vpu,
284 pwrc_ee_is_powered_off, 0, 1),
285 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
286 meson_pwrc_mem_eth),
287 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
288 meson8_pwrc_audio_dsp_mem),
289 };
290
291 static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = {
292 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
293 meson8_pwrc_mem_vpu,
294 pwrc_ee_is_powered_off, 11, 1),
295 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
296 meson_pwrc_mem_eth),
297 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
298 meson8_pwrc_audio_dsp_mem),
299 };
300
301 static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
302 [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
303 pwrc_ee_is_powered_off, 11, 2),
304 [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
305 pwrc_ee_is_powered_off),
306 [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
307 pwrc_ee_is_powered_off),
308 [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
309 pwrc_ee_is_powered_off),
310 [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
311 pwrc_ee_is_powered_off),
312 [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
313 [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
314 };
315
316 struct meson_ee_pwrc_domain {
317 struct generic_pm_domain base;
318 bool enabled;
319 struct meson_ee_pwrc *pwrc;
320 struct meson_ee_pwrc_domain_desc desc;
321 struct clk_bulk_data *clks;
322 int num_clks;
323 struct reset_control *rstc;
324 int num_rstc;
325 };
326
327 struct meson_ee_pwrc {
328 struct regmap *regmap_ao;
329 struct regmap *regmap_hhi;
330 struct meson_ee_pwrc_domain *domains;
331 struct genpd_onecell_data xlate;
332 };
333
pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain * pwrc_domain)334 static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain)
335 {
336 u32 reg;
337
338 regmap_read(pwrc_domain->pwrc->regmap_ao,
339 pwrc_domain->desc.top_pd->sleep_reg, ®);
340
341 return (reg & pwrc_domain->desc.top_pd->sleep_mask);
342 }
343
meson_ee_pwrc_off(struct generic_pm_domain * domain)344 static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
345 {
346 struct meson_ee_pwrc_domain *pwrc_domain =
347 container_of(domain, struct meson_ee_pwrc_domain, base);
348 int i;
349
350 if (pwrc_domain->desc.top_pd)
351 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
352 pwrc_domain->desc.top_pd->sleep_reg,
353 pwrc_domain->desc.top_pd->sleep_mask,
354 pwrc_domain->desc.top_pd->sleep_mask);
355 udelay(20);
356
357 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
358 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
359 pwrc_domain->desc.mem_pd[i].reg,
360 pwrc_domain->desc.mem_pd[i].mask,
361 pwrc_domain->desc.mem_pd[i].mask);
362
363 udelay(20);
364
365 if (pwrc_domain->desc.top_pd)
366 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
367 pwrc_domain->desc.top_pd->iso_reg,
368 pwrc_domain->desc.top_pd->iso_mask,
369 pwrc_domain->desc.top_pd->iso_mask);
370
371 if (pwrc_domain->num_clks) {
372 msleep(20);
373 clk_bulk_disable_unprepare(pwrc_domain->num_clks,
374 pwrc_domain->clks);
375 }
376
377 return 0;
378 }
379
meson_ee_pwrc_on(struct generic_pm_domain * domain)380 static int meson_ee_pwrc_on(struct generic_pm_domain *domain)
381 {
382 struct meson_ee_pwrc_domain *pwrc_domain =
383 container_of(domain, struct meson_ee_pwrc_domain, base);
384 int i, ret;
385
386 if (pwrc_domain->desc.top_pd)
387 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
388 pwrc_domain->desc.top_pd->sleep_reg,
389 pwrc_domain->desc.top_pd->sleep_mask, 0);
390 udelay(20);
391
392 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
393 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
394 pwrc_domain->desc.mem_pd[i].reg,
395 pwrc_domain->desc.mem_pd[i].mask, 0);
396
397 udelay(20);
398
399 ret = reset_control_assert(pwrc_domain->rstc);
400 if (ret)
401 return ret;
402
403 if (pwrc_domain->desc.top_pd)
404 regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
405 pwrc_domain->desc.top_pd->iso_reg,
406 pwrc_domain->desc.top_pd->iso_mask, 0);
407
408 ret = reset_control_deassert(pwrc_domain->rstc);
409 if (ret)
410 return ret;
411
412 return clk_bulk_prepare_enable(pwrc_domain->num_clks,
413 pwrc_domain->clks);
414 }
415
meson_ee_pwrc_init_domain(struct platform_device * pdev,struct meson_ee_pwrc * pwrc,struct meson_ee_pwrc_domain * dom)416 static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
417 struct meson_ee_pwrc *pwrc,
418 struct meson_ee_pwrc_domain *dom)
419 {
420 int ret;
421
422 dom->pwrc = pwrc;
423 dom->num_rstc = dom->desc.reset_names_count;
424 dom->num_clks = dom->desc.clk_names_count;
425
426 if (dom->num_rstc) {
427 int count = reset_control_get_count(&pdev->dev);
428
429 if (count != dom->num_rstc)
430 dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n",
431 count, dom->desc.name);
432
433 dom->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
434 if (IS_ERR(dom->rstc))
435 return PTR_ERR(dom->rstc);
436 }
437
438 if (dom->num_clks) {
439 int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks);
440 if (ret < 0)
441 return ret;
442
443 if (dom->num_clks != ret) {
444 dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n",
445 ret, dom->desc.name);
446 dom->num_clks = ret;
447 }
448 }
449
450 dom->base.name = dom->desc.name;
451 dom->base.power_on = meson_ee_pwrc_on;
452 dom->base.power_off = meson_ee_pwrc_off;
453
454 /*
455 * TOFIX: This is a special case for the VPU power domain, which can
456 * be enabled previously by the bootloader. In this case the VPU
457 * pipeline may be functional but no driver maybe never attach
458 * to this power domain, and if the domain is disabled it could
459 * cause system errors. This is why the pm_domain_always_on_gov
460 * is used here.
461 * For the same reason, the clocks should be enabled in case
462 * we need to power the domain off, otherwise the internal clocks
463 * prepare/enable counters won't be in sync.
464 */
465 if (dom->num_clks && dom->desc.is_powered_off && !dom->desc.is_powered_off(dom)) {
466 ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks);
467 if (ret)
468 return ret;
469
470 dom->base.flags = GENPD_FLAG_ALWAYS_ON;
471 ret = pm_genpd_init(&dom->base, NULL, false);
472 if (ret)
473 return ret;
474 } else {
475 ret = pm_genpd_init(&dom->base, NULL,
476 (dom->desc.is_powered_off ?
477 dom->desc.is_powered_off(dom) : true));
478 if (ret)
479 return ret;
480 }
481
482 return 0;
483 }
484
meson_ee_pwrc_probe(struct platform_device * pdev)485 static int meson_ee_pwrc_probe(struct platform_device *pdev)
486 {
487 const struct meson_ee_pwrc_domain_data *match;
488 struct regmap *regmap_ao, *regmap_hhi;
489 struct device_node *parent_np;
490 struct meson_ee_pwrc *pwrc;
491 int i, ret;
492
493 match = of_device_get_match_data(&pdev->dev);
494 if (!match) {
495 dev_err(&pdev->dev, "failed to get match data\n");
496 return -ENODEV;
497 }
498
499 pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
500 if (!pwrc)
501 return -ENOMEM;
502
503 pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
504 sizeof(*pwrc->xlate.domains),
505 GFP_KERNEL);
506 if (!pwrc->xlate.domains)
507 return -ENOMEM;
508
509 pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
510 sizeof(*pwrc->domains), GFP_KERNEL);
511 if (!pwrc->domains)
512 return -ENOMEM;
513
514 pwrc->xlate.num_domains = match->count;
515
516 parent_np = of_get_parent(pdev->dev.of_node);
517 regmap_hhi = syscon_node_to_regmap(parent_np);
518 of_node_put(parent_np);
519 if (IS_ERR(regmap_hhi)) {
520 dev_err(&pdev->dev, "failed to get HHI regmap\n");
521 return PTR_ERR(regmap_hhi);
522 }
523
524 regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
525 "amlogic,ao-sysctrl");
526 if (IS_ERR(regmap_ao)) {
527 dev_err(&pdev->dev, "failed to get AO regmap\n");
528 return PTR_ERR(regmap_ao);
529 }
530
531 pwrc->regmap_ao = regmap_ao;
532 pwrc->regmap_hhi = regmap_hhi;
533
534 platform_set_drvdata(pdev, pwrc);
535
536 for (i = 0 ; i < match->count ; ++i) {
537 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
538
539 memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc));
540
541 ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom);
542 if (ret)
543 return ret;
544
545 pwrc->xlate.domains[i] = &dom->base;
546 }
547
548 return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
549 }
550
meson_ee_pwrc_shutdown(struct platform_device * pdev)551 static void meson_ee_pwrc_shutdown(struct platform_device *pdev)
552 {
553 struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev);
554 int i;
555
556 for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) {
557 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
558
559 if (dom->desc.is_powered_off && !dom->desc.is_powered_off(dom))
560 meson_ee_pwrc_off(&dom->base);
561 }
562 }
563
564 static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
565 .count = ARRAY_SIZE(g12a_pwrc_domains),
566 .domains = g12a_pwrc_domains,
567 };
568
569 static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = {
570 .count = ARRAY_SIZE(axg_pwrc_domains),
571 .domains = axg_pwrc_domains,
572 };
573
574 static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
575 .count = ARRAY_SIZE(gxbb_pwrc_domains),
576 .domains = gxbb_pwrc_domains,
577 };
578
579 static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = {
580 .count = ARRAY_SIZE(meson8_pwrc_domains),
581 .domains = meson8_pwrc_domains,
582 };
583
584 static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = {
585 .count = ARRAY_SIZE(meson8b_pwrc_domains),
586 .domains = meson8b_pwrc_domains,
587 };
588
589 static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
590 .count = ARRAY_SIZE(sm1_pwrc_domains),
591 .domains = sm1_pwrc_domains,
592 };
593
594 static const struct of_device_id meson_ee_pwrc_match_table[] = {
595 {
596 .compatible = "amlogic,meson8-pwrc",
597 .data = &meson_ee_m8_pwrc_data,
598 },
599 {
600 .compatible = "amlogic,meson8b-pwrc",
601 .data = &meson_ee_m8b_pwrc_data,
602 },
603 {
604 .compatible = "amlogic,meson8m2-pwrc",
605 .data = &meson_ee_m8b_pwrc_data,
606 },
607 {
608 .compatible = "amlogic,meson-axg-pwrc",
609 .data = &meson_ee_axg_pwrc_data,
610 },
611 {
612 .compatible = "amlogic,meson-gxbb-pwrc",
613 .data = &meson_ee_gxbb_pwrc_data,
614 },
615 {
616 .compatible = "amlogic,meson-g12a-pwrc",
617 .data = &meson_ee_g12a_pwrc_data,
618 },
619 {
620 .compatible = "amlogic,meson-sm1-pwrc",
621 .data = &meson_ee_sm1_pwrc_data,
622 },
623 { /* sentinel */ }
624 };
625 MODULE_DEVICE_TABLE(of, meson_ee_pwrc_match_table);
626
627 static struct platform_driver meson_ee_pwrc_driver = {
628 .probe = meson_ee_pwrc_probe,
629 .shutdown = meson_ee_pwrc_shutdown,
630 .driver = {
631 .name = "meson_ee_pwrc",
632 .of_match_table = meson_ee_pwrc_match_table,
633 },
634 };
635 module_platform_driver(meson_ee_pwrc_driver);
636 MODULE_LICENSE("GPL v2");
637