1 /*
2 * Copyright (c) 2012-2015 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <lk/err.h>
9 #include <lk/debug.h>
10 #include <stdio.h>
11 #include <string.h>
12 #include <arch/arm/mmu.h>
13 #include <kernel/vm.h>
14 #include <dev/uart.h>
15 #include <dev/interrupt/arm_gic.h>
16 #include <dev/timer/arm_cortex_a9.h>
17 #include <lk/console_cmd.h>
18 #include <lib/watchdog.h>
19 #include <platform.h>
20 #include <platform/zynq.h>
21 #include <platform/gem.h>
22 #include <platform/timer.h>
23 #include "platform_p.h"
24
25 #if ZYNQ_SDRAM_INIT
26 STATIC_ASSERT(SDRAM_SIZE != 0);
27 #endif
28
29 /* default timeout of the global hardware watchdog */
30 #ifndef ZYNQ_WATCHDOG_TIMEOUT
31 #define ZYNQ_WATCHDOG_TIMEOUT (1000) // 1 second
32 #endif
33
34 /* saved REBOOT_STATUS register */
35 static uint32_t saved_reboot_status;
36
37 /* target can specify this as the initial jam table to set up the soc */
38 void ps7_init(void);
ps7_init(void)39 __WEAK void ps7_init(void) { }
40
41 /* These should be defined in the target somewhere */
42 extern const uint32_t zynq_mio_cfg[ZYNQ_MIO_CNT];
43 extern const long zynq_ddr_cfg[];
44 extern const uint32_t zynq_ddr_cfg_cnt;
45 extern const zynq_pll_cfg_tree_t zynq_pll_cfg;
46 extern const zynq_clk_cfg_t zynq_clk_cfg;
47 extern const zynq_ddriob_cfg_t zynq_ddriob_cfg;
48
reg_poll(uint32_t addr,uint32_t mask)49 static inline int reg_poll(uint32_t addr,uint32_t mask) {
50 uint32_t iters = UINT_MAX;
51 while (iters-- && !(*REG32(addr) & mask)) ;
52
53 if (iters) {
54 return 0;
55 }
56
57 return -1;
58 }
59
60 /* For each PLL we need to configure the cp / res / lock_cnt and then place the PLL in bypass
61 * before doing a reset to switch to the new values. Then bypass is removed to switch back to using
62 * the PLL once its locked.
63 */
zynq_pll_init(void)64 static int zynq_pll_init(void) {
65 const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
66
67 SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
68 PLL_CFG_PLL_RES(cfg->arm.res);
69 SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(cfg->arm.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
70 SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
71
72 if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_ARM_PLL_LOCK) == -1) {
73 return -1;
74 }
75
76 SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
77 SLCR_REG(ARM_CLK_CTRL) = zynq_clk_cfg.arm_clk;
78
79 #if ZYNQ_SDRAM_INIT
80 SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->ddr.lock_cnt) | PLL_CFG_PLL_CP(cfg->ddr.cp) |
81 PLL_CFG_PLL_RES(cfg->ddr.res);
82 SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
83 SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
84
85 if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_DDR_PLL_LOCK) == -1) {
86 return -1;
87 }
88
89 SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
90 SLCR_REG(DDR_CLK_CTRL) = zynq_clk_cfg.ddr_clk;
91 #elif SDRAM_SIZE == 0
92 /* if we're not using sdram and haven't been told to initialize sdram, stop the DDR pll */
93 SLCR_REG(DDR_CLK_CTRL) = 0;
94 SLCR_REG(DDR_PLL_CTRL) |= PLL_PWRDOWN;
95 #endif
96 SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->io.lock_cnt) | PLL_CFG_PLL_CP(cfg->io.cp) |
97 PLL_CFG_PLL_RES(cfg->io.res);
98 SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(cfg->io.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
99 SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
100
101 if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_IO_PLL_LOCK) == -1) {
102 return -1;
103 }
104
105 SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
106 return 0;
107 }
108
zynq_mio_init(void)109 static int zynq_mio_init(void) {
110
111 /* This DDRIOB configuration applies to both zybo and uzed, but it's possible
112 * it may not work for all boards in the future. Just something to keep in mind
113 * with different memory configurations.
114 */
115 SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN;
116
117 for (size_t pin = 0; pin < countof(zynq_mio_cfg); pin++) {
118 if (zynq_mio_cfg[pin] != MIO_DEFAULT) {
119 SLCR_REG(MIO_PIN_00 + (pin * 4)) = zynq_mio_cfg[pin];
120 }
121 }
122
123 SLCR_REG(SD0_WP_CD_SEL) = SDIO0_WP_SEL(0x37) | SDIO0_CD_SEL(0x2F);
124
125 return 0;
126 }
127
zynq_clk_init(void)128 static void zynq_clk_init(void) {
129 SLCR_REG(DCI_CLK_CTRL) = zynq_clk_cfg.dci_clk;
130 SLCR_REG(GEM0_CLK_CTRL) = zynq_clk_cfg.gem0_clk;
131 SLCR_REG(GEM0_RCLK_CTRL) = zynq_clk_cfg.gem0_rclk;
132 SLCR_REG(GEM1_CLK_CTRL) = zynq_clk_cfg.gem1_clk;
133 SLCR_REG(GEM1_RCLK_CTRL) = zynq_clk_cfg.gem1_rclk;
134 SLCR_REG(SMC_CLK_CTRL) = zynq_clk_cfg.smc_clk;
135 SLCR_REG(LQSPI_CLK_CTRL) = zynq_clk_cfg.lqspi_clk;
136 SLCR_REG(SDIO_CLK_CTRL) = zynq_clk_cfg.sdio_clk;
137 SLCR_REG(UART_CLK_CTRL) = zynq_clk_cfg.uart_clk;
138 SLCR_REG(SPI_CLK_CTRL) = zynq_clk_cfg.spi_clk;
139 SLCR_REG(CAN_CLK_CTRL) = zynq_clk_cfg.can_clk;
140 SLCR_REG(CAN_MIOCLK_CTRL)= zynq_clk_cfg.can_mioclk;
141 SLCR_REG(USB0_CLK_CTRL) = zynq_clk_cfg.usb0_clk;
142 SLCR_REG(USB1_CLK_CTRL) = zynq_clk_cfg.usb1_clk;
143 SLCR_REG(PCAP_CLK_CTRL) = zynq_clk_cfg.pcap_clk;
144 SLCR_REG(FPGA0_CLK_CTRL) = zynq_clk_cfg.fpga0_clk;
145 SLCR_REG(FPGA1_CLK_CTRL) = zynq_clk_cfg.fpga1_clk;
146 SLCR_REG(FPGA2_CLK_CTRL) = zynq_clk_cfg.fpga2_clk;
147 SLCR_REG(FPGA3_CLK_CTRL) = zynq_clk_cfg.fpga3_clk;
148 SLCR_REG(APER_CLK_CTRL) = zynq_clk_cfg.aper_clk;
149 SLCR_REG(CLK_621_TRUE) = zynq_clk_cfg.clk_621_true;
150 }
151
152 #if ZYNQ_SDRAM_INIT
zynq_ddr_init(void)153 static void zynq_ddr_init(void) {
154 SLCR_REG(DDRIOB_ADDR0) = zynq_ddriob_cfg.addr0;
155 SLCR_REG(DDRIOB_ADDR1) = zynq_ddriob_cfg.addr1;
156 SLCR_REG(DDRIOB_DATA0) = zynq_ddriob_cfg.data0;
157 SLCR_REG(DDRIOB_DATA1) = zynq_ddriob_cfg.data1;
158 SLCR_REG(DDRIOB_DIFF0) = zynq_ddriob_cfg.diff0;
159 SLCR_REG(DDRIOB_DIFF1) = zynq_ddriob_cfg.diff1;
160 SLCR_REG(DDRIOB_CLOCK) = DDRIOB_OUTPUT_EN(0x3);
161
162 /* These register fields are not documented in the TRM. These
163 * values represent the defaults generated via the Zynq tools
164 */
165 SLCR_REG(DDRIOB_DRIVE_SLEW_ADDR) = 0x0018C61CU;
166 SLCR_REG(DDRIOB_DRIVE_SLEW_DATA) = 0x00F9861CU;
167 SLCR_REG(DDRIOB_DRIVE_SLEW_DIFF) = 0x00F9861CU;
168 SLCR_REG(DDRIOB_DRIVE_SLEW_CLOCK) = 0x00F9861CU;
169 SLCR_REG(DDRIOB_DDR_CTRL) = 0x00000E60U;
170 SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U;
171 SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U;
172 SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000823U;
173
174 /* Write addresss / value pairs from target table */
175 for (size_t i = 0; i < zynq_ddr_cfg_cnt; i += 2) {
176 *REG32(zynq_ddr_cfg[i]) = zynq_ddr_cfg[i+1];
177 }
178
179 /* Wait for DCI done */
180 reg_poll((uintptr_t)&SLCR->DDRIOB_DCI_STATUS, 0x2000);
181
182 /* Bring ddr out of reset and wait until self refresh */
183 *REG32(DDRC_CTRL) |= DDRC_CTRL_OUT_OF_RESET;
184 reg_poll(DDRC_MODE_STATUS, DDRC_STS_SELF_REFRESH);
185
186 /* Switch timer to 64k */
187 *REG32(0XF8007000) = *REG32(0xF8007000) & ~0x20000000U;
188
189 if (zynq_ddriob_cfg.ibuf_disable) {
190 SLCR_REG(DDRIOB_DATA0) |= DDRIOB_IBUF_DISABLE_MODE;
191 SLCR_REG(DDRIOB_DATA1) |= DDRIOB_IBUF_DISABLE_MODE;
192 SLCR_REG(DDRIOB_DIFF0) |= DDRIOB_IBUF_DISABLE_MODE;
193 SLCR_REG(DDRIOB_DIFF1) |= DDRIOB_IBUF_DISABLE_MODE;
194 }
195
196 if (zynq_ddriob_cfg.term_disable) {
197 SLCR_REG(DDRIOB_DATA0) |= DDRIOB_TERM_DISABLE_MODE;
198 SLCR_REG(DDRIOB_DATA1) |= DDRIOB_TERM_DISABLE_MODE;
199 SLCR_REG(DDRIOB_DIFF0) |= DDRIOB_TERM_DISABLE_MODE;
200 SLCR_REG(DDRIOB_DIFF1) |= DDRIOB_TERM_DISABLE_MODE;
201 }
202 }
203 #endif
204
205 STATIC_ASSERT(IS_ALIGNED(SDRAM_BASE, MB));
206 STATIC_ASSERT(IS_ALIGNED(SDRAM_SIZE, MB));
207
208 #if SDRAM_SIZE != 0
209 /* if we have sdram, the first 1MB is covered by sram */
210 #define RAM_SIZE (MB + (SDRAM_SIZE - MB))
211 #else
212 #define RAM_SIZE (MB)
213 #endif
214
215 /* initial memory mappings. parsed by start.S */
216 struct mmu_initial_mapping mmu_initial_mappings[] = {
217 /* 1GB of sram + sdram space */
218 {
219 .phys = SRAM_BASE,
220 .virt = KERNEL_BASE,
221 .size = RAM_SIZE,
222 .flags = 0,
223 .name = "memory"
224 },
225
226 /* AXI fpga fabric bus 0 */
227 {
228 .phys = 0x40000000,
229 .virt = 0x40000000,
230 .size = (128*1024*1024),
231 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
232 .name = "axi0"
233 },
234
235 /* AXI fpga fabric bus 1 */
236 {
237 .phys = 0x80000000,
238 .virt = 0x80000000,
239 .size = (16*1024*1024),
240 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
241 .name = "axi1"
242 },
243 /* 0xe0000000 hardware devices */
244 {
245 .phys = 0xe0000000,
246 .virt = 0xe0000000,
247 .size = 0x00300000,
248 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
249 .name = "hw-e0000000"
250 },
251
252 /* 0xe1000000 hardware devices */
253 {
254 .phys = 0xe1000000,
255 .virt = 0xe1000000,
256 .size = 0x05000000,
257 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
258 .name = "hw-e1000000"
259 },
260
261 /* 0xf8000000 hardware devices */
262 {
263 .phys = 0xf8000000,
264 .virt = 0xf8000000,
265 .size = 0x01000000,
266 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
267 .name = "hw-f8000000"
268 },
269
270 /* 0xfc000000 hardware devices */
271 {
272 .phys = 0xfc000000,
273 .virt = 0xfc000000,
274 .size = 0x02000000,
275 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
276 .name = "hw-fc000000"
277 },
278
279 /* sram high aperture */
280 {
281 .phys = 0xfff00000,
282 .virt = 0xfff00000,
283 .size = 0x00100000,
284 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE
285 },
286
287 /* identity map to let the boot code run */
288 {
289 .phys = SRAM_BASE,
290 .virt = SRAM_BASE,
291 .size = RAM_SIZE,
292 .flags = MMU_INITIAL_MAPPING_TEMPORARY
293 },
294
295 /* null entry to terminate the list */
296 { 0 }
297 };
298
299 #if SDRAM_SIZE != 0
300 static pmm_arena_t sdram_arena = {
301 .name = "sdram",
302 .base = SDRAM_BASE,
303 .size = SDRAM_SIZE - MB, /* first 1MB is covered by SRAM */
304 .flags = PMM_ARENA_FLAG_KMAP
305 };
306 #endif
307
308 static pmm_arena_t sram_arena = {
309 .name = "sram",
310 .base = SRAM_BASE,
311 .size = SRAM_SIZE,
312 .priority = 1,
313 .flags = PMM_ARENA_FLAG_KMAP
314 };
315
platform_init_mmu_mappings(void)316 void platform_init_mmu_mappings(void) {
317 }
318
platform_early_init(void)319 void platform_early_init(void) {
320 #if 0
321 ps7_init();
322 #else
323 /* Unlock the registers and leave them that way */
324 zynq_slcr_unlock();
325 zynq_mio_init();
326 zynq_pll_init();
327 zynq_clk_init();
328 #if ZYNQ_SDRAM_INIT
329 zynq_ddr_init();
330 #endif
331 #endif
332
333 /* Enable all level shifters */
334 SLCR_REG(LVL_SHFTR_EN) = 0xF;
335 /* FPGA SW reset (not documented, but mandatory) */
336 SLCR_REG(FPGA_RST_CTRL) = 0x0;
337
338 /* zynq manual says this is mandatory for cache init */
339 *REG32(SLCR_BASE + 0xa1c) = 0x020202;
340
341 /* save the reboot status register, clear bits we dont want to save */
342 saved_reboot_status = SLCR->REBOOT_STATUS;
343 SLCR->REBOOT_STATUS &= ~(0xff << 16);
344
345 /* early initialize the uart so we can printf */
346 uart_init_early();
347
348 /* initialize the interrupt controller */
349 arm_gic_init();
350 zynq_gpio_init();
351
352 /* initialize the timer block */
353 arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq());
354
355 /* initialize the hardware watchdog */
356 watchdog_hw_init(ZYNQ_WATCHDOG_TIMEOUT);
357
358 /* bump the 2nd cpu into our code space and remap the top SRAM block */
359 if (KERNEL_LOAD_OFFSET != 0) {
360 /* construct a trampoline to get the 2nd cpu up to the trap routine */
361
362 /* figure out the offset of the trampoline routine in physical space from address 0 */
363 extern void platform_reset(void);
364 addr_t tramp = (addr_t)&platform_reset;
365 tramp -= KERNEL_BASE;
366 tramp += MEMBASE;
367
368 /* stuff in a ldr pc, [nextaddrress], and a target address */
369 uint32_t *ptr = (uint32_t *)KERNEL_BASE;
370
371 ptr[0] = 0xe51ff004; // ldr pc, [pc, #-4]
372 ptr[1] = tramp;
373 arch_clean_invalidate_cache_range((addr_t)ptr, 8);
374 }
375
376 /* reset the 2nd cpu, letting it go through its reset vector (at 0x0 physical) */
377 SLCR_REG(A9_CPU_RST_CTRL) |= (1<<1); // reset cpu 1
378 spin(10);
379 SLCR_REG(A9_CPU_RST_CTRL) &= ~(1<<1); // unreset cpu 1
380
381 /* wait for the 2nd cpu to reset, go through the usual reset vector, and get trapped by our code */
382 /* see platform/zynq/reset.S */
383 extern volatile int __cpu_trapped;
384 uint count = 100000;
385 while (--count) {
386 arch_clean_invalidate_cache_range((addr_t)&__cpu_trapped, sizeof(__cpu_trapped));
387 if (__cpu_trapped != 0)
388 break;
389 }
390 if (count == 0) {
391 panic("ZYNQ: failed to trap 2nd cpu\n");
392 }
393
394 /* bounce the 4th sram region down to lower address */
395 SLCR_REG(OCM_CFG) &= ~0xf; /* all banks at low address */
396
397 /* add the main memory arena */
398 #if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0
399 /* In the case of running from SRAM, and we are using SDRAM,
400 * there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB),
401 * so intentionally bump the boot-time allocator to start in the base of SDRAM.
402 */
403 extern uintptr_t boot_alloc_start;
404 extern uintptr_t boot_alloc_end;
405
406 boot_alloc_start = KERNEL_BASE + MB;
407 boot_alloc_end = KERNEL_BASE + MB;
408 #endif
409
410 #if SDRAM_SIZE != 0
411 pmm_add_arena(&sdram_arena);
412 #endif
413 pmm_add_arena(&sram_arena);
414 }
415
platform_init(void)416 void platform_init(void) {
417 uart_init();
418
419 /* enable if we want to see some hardware boot status */
420 #if LK_DEBUGLEVEL > 0
421 printf("zynq boot status:\n");
422 printf("\tREBOOT_STATUS 0x%x\n", saved_reboot_status);
423 if (BIT(saved_reboot_status, 16)) printf("\t\tSWDT_RST\n");
424 if (BIT(saved_reboot_status, 17)) printf("\t\tAWDT0_RST\n");
425 if (BIT(saved_reboot_status, 18)) printf("\t\tAWDT1_RST\n");
426 if (BIT(saved_reboot_status, 19)) printf("\t\tSLC_RST\n");
427 if (BIT(saved_reboot_status, 20)) printf("\t\tDBG_RST\n");
428 if (BIT(saved_reboot_status, 21)) printf("\t\tSRST_B\n");
429 if (BIT(saved_reboot_status, 22)) printf("\t\tPOR\n");
430 printf("\tREBOOT_STATE 0x%lx\n", BITS_SHIFT(saved_reboot_status, 31, 24));
431 printf("\tboot mode 0x%x\n", zynq_get_boot_mode());
432 #endif
433 }
434
platform_quiesce(void)435 void platform_quiesce(void) {
436 #if ZYNQ_WITH_GEM_ETH
437 gem_disable();
438 #endif
439
440 platform_stop_timer();
441
442 /* stop the 2nd cpu and hold in reset */
443 SLCR_REG(A9_CPU_RST_CTRL) |= (1<<1); // reset cpu 1
444 }
445
446 /* called from lkboot to see if we want to abort autobooting.
447 * having the BOOT_MODE pins set to JTAG should cause us to hang out in
448 * whatever binary is loaded at the time.
449 */
450 bool platform_abort_autoboot(void);
platform_abort_autoboot(void)451 bool platform_abort_autoboot(void) {
452 /* test BOOT_MODE pins to see if we want to skip the autoboot stuff */
453 uint32_t boot_mode = zynq_get_boot_mode();
454 if (boot_mode == ZYNQ_BOOT_MODE_JTAG) {
455 printf("ZYNQ: disabling autoboot due to JTAG/QSPI jumper being set to JTAG\n");
456 return true;
457 }
458
459 return false;
460 }
461
cmd_zynq(int argc,const console_cmd_args * argv)462 static int cmd_zynq(int argc, const console_cmd_args *argv) {
463 if (argc < 2) {
464 notenoughargs:
465 printf("not enough arguments\n");
466 usage:
467 printf("usage: %s <command>\n", argv[0].str);
468 printf("\tslcr lock\n");
469 printf("\tslcr unlock\n");
470 printf("\tslcr lockstatus\n");
471 printf("\tmio\n");
472 printf("\tclocks\n");
473 printf("\ttrip_watchdog\n");
474 return -1;
475 }
476
477 if (!strcmp(argv[1].str, "slcr")) {
478 if (argc < 3) goto notenoughargs;
479
480 bool print_lock_status = false;
481 if (!strcmp(argv[2].str, "lock")) {
482 zynq_slcr_lock();
483 print_lock_status = true;
484 } else if (!strcmp(argv[2].str, "unlock")) {
485 zynq_slcr_unlock();
486 print_lock_status = true;
487 } else if (print_lock_status || !strcmp(argv[2].str, "lockstatus")) {
488 printf("%s\n", (SLCR->SLCR_LOCKSTA & 0x1) ? "locked" : "unlocked");
489 } else {
490 goto usage;
491 }
492 } else if (!strcmp(argv[1].str, "mio")) {
493 printf("zynq mio:\n");
494 for (size_t i = 0; i < ZYNQ_MIO_CNT; i++) {
495 printf("\t%02u: 0x%08x", i, *REG32((uintptr_t)&SLCR->MIO_PIN_00 + (i * 4)));
496 if (i % 4 == 3 || i == 53) {
497 putchar('\n');
498 }
499 }
500 } else if (!strcmp(argv[1].str, "clocks")) {
501 zynq_dump_clocks();
502 } else if (!strcmp(argv[1].str, "trip_watchdog")) {
503 /* try to trip the watchdog by disabling interrupts for a while */
504 arch_disable_ints();
505 for (int i = 0; i < 20; i++) {
506 spin(250000);
507 printf("SWDT MODE 0x%x CONTROL 0x%x STATUS 0x%x\n", SWDT->MODE, SWDT->CONTROL, SWDT->STATUS);
508 }
509 arch_enable_ints();
510 } else {
511 goto usage;
512 }
513
514 return 0;
515 }
516
517 STATIC_COMMAND_START
518 #if LK_DEBUGLEVEL > 1
519 STATIC_COMMAND("zynq", "zynq configuration commands", &cmd_zynq)
520 #endif
521 STATIC_COMMAND_END(zynq);
522