Searched refs:DMA_CRL3 (Results 1 – 2 of 2) sorted by relevance
94 if((psdioh->SD_TRANSFER & SDIOH_TRANSFER_END) && (!(psdioh->DMA_CRL3 & SDIOH_DMA_XFER))) { in SDIOH_WaitDMADone()245 psdioh->DMA_CRL3 = tmp; in SDIOH_DMAConfig()251 tmp = psdioh->DMA_CRL3; in SDIOH_DMAConfig()253 psdioh->DMA_CRL3 = tmp; in SDIOH_DMAConfig()271 psdioh->DMA_CRL3 = 0; in SDIOH_DMAReset()
1378 __IO uint32_t DMA_CRL3; /*!< DMA Control Register 3, Address offset: 0x0000040C*/ member
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