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/AliOS-Things-master/components/amp/test/host/
A DtcpServer.js4 var PORT = 50000; variable
7 server.listen(PORT, HOST);
9 console.log('Server listening on ' + HOST + ':' + PORT);
/AliOS-Things-master/components/py_engine/tests/multi_net/
A Dtcp_accept_recv.py5 PORT = 8000 variable
13 s.bind(socket.getaddrinfo("0.0.0.0", PORT)[0][-1])
28 s.connect(socket.getaddrinfo(IP, PORT)[0][-1])
A Dtcp_data.py5 PORT = 8000 variable
12 s.bind(socket.getaddrinfo("0.0.0.0", PORT)[0][-1])
25 s.connect(socket.getaddrinfo(IP, PORT)[0][-1])
A Dssl_data.py6 PORT = 8000 variable
14 s.bind(socket.getaddrinfo("0.0.0.0", PORT)[0][-1])
28 s.connect(socket.getaddrinfo(IP, PORT)[0][-1])
A Duasyncio_tcp_close_write.py12 PORT = 8000 variable
35 server = await asyncio.start_server(handle_connection, "0.0.0.0", PORT)
43 reader, writer = await asyncio.open_connection(IP, PORT)
A Duasyncio_tcp_server_client.py12 PORT = 8000 variable
35 server = await asyncio.start_server(handle_connection, "0.0.0.0", PORT)
43 reader, writer = await asyncio.open_connection(IP, PORT)
A Duasyncio_tcp_client_rst.py14 PORT = 8000 variable
34 server = await asyncio.start_server(handle_connection, "0.0.0.0", PORT)
50 s.connect(socket.getaddrinfo(IP, PORT)[0][-1])
A Duasyncio_tcp_readexactly.py12 PORT = 8000 variable
42 server = await asyncio.start_server(handle_connection, "0.0.0.0", PORT)
50 reader, writer = await asyncio.open_connection(IP, PORT)
A Dtcp_client_rst.py5 PORT = 8000 variable
18 s.bind(socket.getaddrinfo("0.0.0.0", PORT)[0][-1])
50 s.connect(socket.getaddrinfo(IP, PORT)[0][-1])
/AliOS-Things-master/components/lwip/example/
A Dudp_test.c10 #define PORT 6666 macro
26 svraddr.sin_port=htons(PORT); in udp_server_task()
63 svraddr.sin_port=htons(PORT); in udp_client_task()
/AliOS-Things-master/hardware/chip/rtl872xd/tools/DownloadServer/
A Dreadme.txt4 DownloadServer "PORT" "FILE_PATH"
/AliOS-Things-master/hardware/chip/rtl872xd/tools/DownloadServer(HTTP)/
A Dreadme.txt4 DownloadServer "PORT" "FILE_PATH"
/AliOS-Things-master/components/py_engine/engine/extmod/
A Dextmod.cmake73 ${MICROPY_LIB_BERKELEY_DIR}/PORT/include
87 "${MICROPY_LIB_BERKELEY_DIR}/PORT/include"
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/cmsis/
A Dcore_cm3.h650 …} PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers … member
1611 while (ITM->PORT[0].u32 == 0); in ITM_SendChar()
1612 ITM->PORT[0].u8 = (uint8_t) ch; in ITM_SendChar()
A Dcore_cm4.h680 …} PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers … member
1722 while (ITM->PORT[0].u32 == 0); in ITM_SendChar()
1723 ITM->PORT[0].u8 = (uint8_t) ch; in ITM_SendChar()
/AliOS-Things-master/hardware/chip/haas1000/drivers/platform/cmsis/inc/
A Dcore_cm3.h760 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1874 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1878 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
A Dcore_sc300.h735 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1855 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1859 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
/AliOS-Things-master/components/csi/CMSIS/Core/Include/
A Dcore_cm3.h765 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1883 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1887 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
A Dcore_sc300.h750 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1857 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1861 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
/AliOS-Things-master/components/py_engine/engine/lib/cmsis/inc/
A Dcore_cm3.h760 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1874 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1878 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
A Dcore_sc300.h735 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1855 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1859 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/third_party/cmsis/CMSIS/Core/Include/
A Dcore_cm3.h765 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1883 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1887 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
A Dcore_sc300.h750 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1857 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1861 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
/AliOS-Things-master/components/ai_agent/src/engine/tflite-micro/tensorflow/lite/micro/tools/make/downloads/cmsis/CMSIS/Core/Include/
A Dcore_cm3.h765 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1883 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1887 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
A Dcore_sc300.h750 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ member
1857 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1861 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()

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