Home
last modified time | relevance | path

Searched refs:SDIOH_CLK_DIV_BY_128 (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/
A Drtl8721dhp_sdio_host.c455 SDIOH_CLK_DIV_BY_128 | SDIOH_INITIAL_MODE | SDIOH_SD30_ASYNC_FIFO_RST_N |\ in SDIOH_InitialModeCmd()
464 SDIOH_CLK_DIV_BY_128 | SDIOH_SD30_ASYNC_FIFO_RST_N |\ in SDIOH_InitialModeCmd()
471 SDIOH_CLK_DIV_BY_128 |(SDIOH_BUS_WIDTH_1BIT << SDIOH_SHIFT_BUS_WIDTH); in SDIOH_InitialModeCmd()
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721d_sdioh.h328 #define SDIOH_CLK_DIV_BY_128 0 macro

Completed in 4 milliseconds