Searched refs:PLL (Results 1 – 9 of 9) sorted by relevance
53 #define PLL_STATUS1_CPUPLLLOCK(CORE, PLL) \ argument54 ((uint32_t)((1 << (PLL)) << ((CORE) * 8)))
55 #define PLL_STATUS1_CPUPLLLOCK(CPU, PLL) \ argument56 ((uint32_t)((1 << (PLL)) << ((CPU) * 8)))
36 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in __wrap_arch_exception_reset()
122 SCC->PLL[PLL_IDX_HDLCD].REG1 = in enable_pll()124 SCC->PLL[PLL_IDX_HDLCD].REG0 = in enable_pll()247 SCC->PLL[PLL_IDX_HDLCD].REG0 = (PLL_REG0_PLL_RESET | PLL_REG0_HARD_BYPASS); in juno_hdlcd_set_rate()450 nf = ((SCC->PLL[PLL_IDX_HDLCD].REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_hdlcd_start()451 nr = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_NR) >> PLL_REG1_NR_POS) + 1; in juno_hdlcd_start()452 od = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_hdlcd_start()
423 .pll = &SCC->PLL[PLL_IDX_BIG],428 .pll = &SCC->PLL[PLL_IDX_LITTLE],433 .pll = &SCC->PLL[PLL_IDX_GPU],
46 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_init()
81 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in pll_init()
109 struct pll_reg PLL[PLL_IDX_COUNT]; member
238 - n1sdp: Add dynamic calculations of PLL parameters
Completed in 27 milliseconds