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Searched refs:PLL_REG1_OD (Results 1 – 3 of 3) sorted by relevance

/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Djuno_soc_clock_ram_pll.c100 output_div = ((pll->REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_soc_clock_ram_pll_get()
/SCP-firmware-master/product/juno/include/
A Djuno_scc.h52 #define PLL_REG1_OD UINT32_C(0x00000F00) macro
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A Dmod_juno_hdlcd.c452 od = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_hdlcd_start()

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