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Searched refs:SCC (Results 1 – 25 of 37) sorted by relevance

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/SCP-firmware-master/product/juno/module/juno_soc_clock/src/
A Dmod_juno_soc_clock.c81 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in pll_init()
167 set_source(&SCC->SAXICLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
169 set_div(&SCC->FAXICLK, CLOCK_RATE_SYSCLK / FAXICLK_CLOCK); in juno_soc_clock_init()
170 set_source(&SCC->FAXICLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
173 set_source(&SCC->HDLCDCLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
175 if ((SCC->GPR0 & SCC_GPR0_SKIP_TLX_CLK_SETTING) == 0) { in juno_soc_clock_init()
176 set_source(&SCC->TMIF2XCLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
177 set_source(&SCC->TSIF2XCLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
180 set_source(&SCC->USBHCLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
182 set_source(&SCC->PCIEACLK, CLKSEL_SYSCLK); in juno_soc_clock_init()
[all …]
/SCP-firmware-master/product/n1sdp/src/
A Dn1sdp_core.c33 return ((SCC->PLATFORM_CTRL & SCC_PLATFORM_CTRL_MULTI_CHIP_MODE_MASK) >> in n1sdp_is_multichip_enabled()
39 return ((uint8_t)((SCC->PLATFORM_CTRL & SCC_PLATFORM_CTRL_CHIPID_MASK) >> in n1sdp_get_chipid()
/SCP-firmware-master/product/morello/src/
A Dmorello_core.c34 (SCC->PLATFORM_CTRL & SCC_PLATFORM_CTRL_MULTI_CHIP_MODE_MASK) >> in morello_is_multichip_enabled()
41 (SCC->PLATFORM_CTRL & SCC_PLATFORM_CTRL_CHIPID_MASK) >> in morello_get_chipid()
/SCP-firmware-master/product/juno/module/juno_ddr_phy400/src/
A Dmod_juno_ddr_phy400.c148 SCC->DDR_PHY0_PLL = SCC_DDR_PHY_PLL_BYPASS_EN; in juno_ddr_phy400_config_clk()
149 SCC->DDR_PHY1_PLL = SCC_DDR_PHY_PLL_BYPASS_EN; in juno_ddr_phy400_config_clk()
188 SCC->DDR_PHY0_RETNCTRL = SCC_DDR_PHY_RETNCTRL_ENABLE; in juno_ddr_phy400_config_retention()
189 SCC->DDR_PHY1_RETNCTRL = SCC_DDR_PHY_RETNCTRL_ENABLE; in juno_ddr_phy400_config_retention()
191 SCC->DDR_PHY0_RETNCTRL = SCC_DDR_PHY_RETNCTRL_DISABLE; in juno_ddr_phy400_config_retention()
192 SCC->DDR_PHY1_RETNCTRL = SCC_DDR_PHY_RETNCTRL_DISABLE; in juno_ddr_phy400_config_retention()
/SCP-firmware-master/product/juno/module/juno_rom/src/
A Dmod_juno_rom.c319 if (SCC->GPR1 & SCC_GPR1_BOOT_MAP_ENABLE) { in juno_rom_process_event()
320 ctx.boot_map_little = (SCC->GPR1 & SCC_GPR1_BOOT_MAP_LITTLE) >> in juno_rom_process_event()
322 ctx.boot_map_big = (SCC->GPR1 & SCC_GPR1_BOOT_MAP_BIG) >> in juno_rom_process_event()
327 if (SCC->GPR1 & SCC_GPR1_CRYPTO_DISABLE) { in juno_rom_process_event()
335 if (SCC->GPR1 & SCC_GPR1_CFGEE) { in juno_rom_process_event()
342 if (SCC->GPR1 & SCC_GPR1_CFGTE) { in juno_rom_process_event()
349 if (SCC->NIC400_TLX & SCC_TLX_MST_ENABLE) { in juno_rom_process_event()
354 if (SCC->APP_ALT_BOOT != (uint32_t)0) { in juno_rom_process_event()
355 if ((SCC->APP_ALT_BOOT & (uint32_t)0x3) != (uint32_t)0) { in juno_rom_process_event()
363 (SCC->APP_ALT_BOOT & SCC_APP_ALT_BOOT_ADDR); in juno_rom_process_event()
/SCP-firmware-master/product/morello/scp_ramfw_fvp/
A Dconfig_pik_clock.c474 .divsys_reg = &SCC->SYSAPBCLK_DIV,
486 .divsys_reg = &SCC->SCPNICCLK_DIV,
498 .divsys_reg = &SCC->SCPI2CCLK_DIV,
510 .divsys_reg = &SCC->SCPQSPICLK_DIV,
522 .divsys_reg = &SCC->SENSORCLK_DIV,
534 .divsys_reg = &SCC->MCPNICCLK_DIV,
546 .divsys_reg = &SCC->MCPI2CCLK_DIV,
558 .divsys_reg = &SCC->MCPQSPICLK_DIV,
570 .divsys_reg = &SCC->PCIEAXICLK_DIV,
582 .divsys_reg = &SCC->CCIXAXICLK_DIV,
[all …]
/SCP-firmware-master/product/morello/scp_ramfw_soc/
A Dconfig_pik_clock.c488 .divsys_reg = &SCC->SYSAPBCLK_DIV,
500 .divsys_reg = &SCC->SCPNICCLK_DIV,
512 .divsys_reg = &SCC->SCPI2CCLK_DIV,
524 .divsys_reg = &SCC->SCPQSPICLK_DIV,
536 .divsys_reg = &SCC->SENSORCLK_DIV,
548 .divsys_reg = &SCC->MCPNICCLK_DIV,
560 .divsys_reg = &SCC->MCPI2CCLK_DIV,
572 .divsys_reg = &SCC->MCPQSPICLK_DIV,
584 .divsys_reg = &SCC->PCIEAXICLK_DIV,
596 .divsys_reg = &SCC->CCIXAXICLK_DIV,
[all …]
/SCP-firmware-master/product/n1sdp/scp_ramfw/
A Dconfig_pik_clock.c475 .divsys_reg = &SCC->SYSAPBCLK_DIV,
487 .divsys_reg = &SCC->SCPNICCLK_DIV,
499 .divsys_reg = &SCC->SCPI2CCLK_DIV,
511 .divsys_reg = &SCC->SCPQSPICLK_DIV,
523 .divsys_reg = &SCC->SENSORCLK_DIV,
535 .divsys_reg = &SCC->MCPNICCLK_DIV,
547 .divsys_reg = &SCC->MCPI2CCLK_DIV,
559 .divsys_reg = &SCC->MCPQSPICLK_DIV,
571 .divsys_reg = &SCC->PCIEAXICLK_DIV,
583 .divsys_reg = &SCC->CCIXAXICLK_DIV,
[all …]
/SCP-firmware-master/product/juno/module/juno_soc_clock_ram/src/
A Dmod_juno_soc_clock_ram.c269 clock_sel_set(&SCC->FAXICLK, SCP_CONFIG_STDCLK_CONTROL_CLKSEL_SYSINCLK); in init_juno_soc_clock()
270 clock_sel_set(&SCC->SAXICLK, SCP_CONFIG_STDCLK_CONTROL_CLKSEL_SYSINCLK); in init_juno_soc_clock()
273 if ((SCC->GPR0 & SCC_GPR0_SKIP_TLX_CLK_SETTING) == 0) { in init_juno_soc_clock()
274 clock_sel_set(&SCC->TMIF2XCLK, in init_juno_soc_clock()
276 clock_sel_set(&SCC->TSIF2XCLK, in init_juno_soc_clock()
283 clock_sel_set(&SCC->PXLCLK, SCP_CONFIG_STDCLK_CONTROL_CLKSEL_SYSINCLK); in init_juno_soc_clock()
593 clock_div_set(&SCC->PCIEACLK, SYSINCLK / PCIEACLK_DEFAULT_FREQ); in juno_soc_clock_start()
596 SCC->SYSTEM_CLK_FORCE |= SCC_SYSTEM_CLK_FORCE_FAXICLK; in juno_soc_clock_start()
599 clock_sel_set(&SCC->PXLCLK, SCC_PXLCLK_CLKSEL_PLL); in juno_soc_clock_start()
602 SCC->SYSTEM_CLK_FORCE |= SCC_SYSTEM_CLK_FORCE_HDLCDCLK; in juno_soc_clock_start()
[all …]
A Djuno_soc_clock_ram_pll.c46 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in juno_soc_clock_ram_pll_init()
/SCP-firmware-master/product/juno/scp_ramfw/
A Dconfig_juno_hdlcd.c46 .scc_control = &SCC->HDLCD0_CONTROL,
63 .scc_control = &SCC->HDLCD1_CONTROL,
89 if (SCC->GPR0 & SCC_GPR0_HIGH_PXLCLK_ENABLE) { in juno_hdlcd_get_element_table()
A Dconfig_juno_reset_domain.c20 .reset_reg = &(SCC->VSYS_MANUAL_RESET),
A Dconfig_juno_soc_clock_ram.c423 .pll = &SCC->PLL[PLL_IDX_BIG],
428 .pll = &SCC->PLL[PLL_IDX_LITTLE],
433 .pll = &SCC->PLL[PLL_IDX_GPU],
/SCP-firmware-master/product/juno/module/juno_ram/src/
A Dmod_juno_ram.c153 SCC->PCSM[i].TRICKLE_DELAY = PCSM_TRICKLE_DELAY; in pcsm_configure()
154 SCC->PCSM[i].HAMMER_DELAY = PCSM_HAMMER_DELAY; in pcsm_configure()
155 SCC->PCSM[i].RAM_DELAY = PCSM_RAM_DELAY; in pcsm_configure()
162 SCC->VSYS_MANUAL_RESET = 0; in scc_configure()
164 SCC->DMA_CONTROL0 = 0x0007FFFE; in scc_configure()
166 SCC->SMC_MASK[3] = 0xFF00FF00; in scc_configure()
180 ((SCC->GPR0 & SCC_GPR0_PCIE_AP_MANAGED) == 0)) { in pcie_configure()
/SCP-firmware-master/product/morello/module/morello_system/src/
A Dmod_morello_system.c313 if (SCC->BOOT_GPR1 & 0x1) { in morello_system_fill_platform_info()
322 sds_platform_info.scc_config = SCC->BOOT_GPR1; in morello_system_fill_platform_info()
367 SCC->BOOT_GPR3, in morello_system_init_primary_core()
368 SCC->BOOT_GPR2); in morello_system_init_primary_core()
376 SCC->BOOT_GPR2; in morello_system_init_primary_core()
378 SCC->BOOT_GPR3; in morello_system_init_primary_core()
405 SCC->TRACE_PAD_CTRL0 = UINT32_C(0x3030303); in morello_system_init_primary_core()
406 SCC->TRACE_PAD_CTRL1 = UINT32_C(0x303); in morello_system_init_primary_core()
414 SCC->DISPLAY_PAD_CTRL0 = UINT32_C(0x01010111); in morello_system_init_primary_core()
/SCP-firmware-master/product/n1sdp/include/
A Dn1sdp_scp_pik.h22 #define SCC ((struct scc_reg *)SCP_SCC_BASE) macro
/SCP-firmware-master/product/juno/scp_romfw_bypass/
A Dconfig_sds.c187 if ((SCC->GPR1 & SCC_GPR1_RESET) == SCC_GPR1_RESET_WDOG) { in get_element_table()
192 if (SCC->GPR1 & SCC_GPR1_BOOT_MAP_ENABLE) { in get_element_table()
194 (SCC->GPR1 & SCC_GPR1_PRIMARY_CPU) >> SCC_GPR1_PRIMARY_CPU_POS; in get_element_table()
A Djuno_pll_workaround.c36 SCC->PLL[pll_idx].REG0 &= ~PLL_REG0_PLL_RESET; in __wrap_arch_exception_reset()
/SCP-firmware-master/product/morello/include/
A Dmorello_scp_pik.h26 #define SCC ((struct scc_reg *)SCP_SCC_BASE) macro
/SCP-firmware-master/product/juno/scp_romfw/
A Dconfig_sds.c179 if ((SCC->GPR1 & SCC_GPR1_RESET) == SCC_GPR1_RESET_WDOG) { in get_element_table()
184 if (SCC->GPR1 & SCC_GPR1_BOOT_MAP_ENABLE) { in get_element_table()
186 (SCC->GPR1 & SCC_GPR1_PRIMARY_CPU) >> SCC_GPR1_PRIMARY_CPU_POS; in get_element_table()
/SCP-firmware-master/product/juno/module/juno_hdlcd/src/
A Dmod_juno_hdlcd.c122 SCC->PLL[PLL_IDX_HDLCD].REG1 = in enable_pll()
124 SCC->PLL[PLL_IDX_HDLCD].REG0 = in enable_pll()
247 SCC->PLL[PLL_IDX_HDLCD].REG0 = (PLL_REG0_PLL_RESET | PLL_REG0_HARD_BYPASS); in juno_hdlcd_set_rate()
450 nf = ((SCC->PLL[PLL_IDX_HDLCD].REG0 & PLL_REG0_NF) >> PLL_REG0_NF_POS) + 1; in juno_hdlcd_start()
451 nr = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_NR) >> PLL_REG1_NR_POS) + 1; in juno_hdlcd_start()
452 od = ((SCC->PLL[PLL_IDX_HDLCD].REG1 & PLL_REG1_OD) >> PLL_REG1_OD_POS) + 1; in juno_hdlcd_start()
/SCP-firmware-master/product/morello/module/morello_rom/src/
A Dmod_morello_rom.c139 (SCC->BOOT_GPR0 != 0x0)) { in morello_rom_process_event()
140 fip_base = SCC->BOOT_GPR0; in morello_rom_process_event()
/SCP-firmware-master/product/morello/module/morello_pcie/src/
A Dmod_morello_pcie.c173 SCC->AXI_OVRD_CCIX = AXI_OVRD_VAL_CCIX; in morello_pcie_power_on()
174 SCC->CCIX_PM_CTRL = SCC_CCIX_PM_CTRL_PWR_REQ_POS; in morello_pcie_power_on()
185 SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_CCIX_POS); in morello_pcie_power_on()
187 SCC->AXI_OVRD_PCIE = AXI_OVRD_VAL_PCIE; in morello_pcie_power_on()
188 SCC->PCIE_PM_CTRL = SCC_PCIE_PM_CTRL_PWR_REQ_POS; in morello_pcie_power_on()
199 SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_PCIE_POS); in morello_pcie_power_on()
/SCP-firmware-master/product/n1sdp/module/n1sdp_pcie/src/
A Dmod_n1sdp_pcie.c172 SCC->AXI_OVRD_CCIX = AXI_OVRD_VAL_CCIX; in n1sdp_pcie_power_on()
173 SCC->CCIX_PM_CTRL = SCC_CCIX_PM_CTRL_PWR_REQ_POS; in n1sdp_pcie_power_on()
184 SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_CCIX_POS); in n1sdp_pcie_power_on()
186 SCC->AXI_OVRD_PCIE = AXI_OVRD_VAL_PCIE; in n1sdp_pcie_power_on()
187 SCC->PCIE_PM_CTRL = SCC_PCIE_PM_CTRL_PWR_REQ_POS; in n1sdp_pcie_power_on()
198 SCC->SYS_MAN_RESET &= ~(1 << SCC_SYS_MAN_RESET_PCIE_POS); in n1sdp_pcie_power_on()
/SCP-firmware-master/product/juno/src/
A Djuno_id.c34 plat = (SCC->GPR0 & SCC_GPR0_PLATFORM_ID_PLAT) >> in juno_id_get_platform()

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