Searched refs:ref_rate (Results 1 – 7 of 7) sorted by relevance
| /SCP-firmware-master/product/morello/scp_ramfw_soc/ |
| A D | config_morello_pll.c | 27 .ref_rate = CLOCK_RATE_REFCLK,
36 .ref_rate = CLOCK_RATE_REFCLK,
45 .ref_rate = CLOCK_RATE_REFCLK,
54 .ref_rate = CLOCK_RATE_REFCLK,
63 .ref_rate = CLOCK_RATE_REFCLK,
72 .ref_rate = CLOCK_RATE_REFCLK,
81 .ref_rate = CLOCK_RATE_REFCLK,
90 .ref_rate = CLOCK_RATE_REFCLK,
99 .ref_rate = CLOCK_RATE_REFCLK,
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| /SCP-firmware-master/product/n1sdp/scp_ramfw/ |
| A D | config_n1sdp_pll.c | 26 .ref_rate = CLOCK_RATE_REFCLK,
35 .ref_rate = CLOCK_RATE_REFCLK,
44 .ref_rate = CLOCK_RATE_REFCLK,
53 .ref_rate = CLOCK_RATE_REFCLK,
62 .ref_rate = CLOCK_RATE_REFCLK,
71 .ref_rate = CLOCK_RATE_REFCLK,
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| /SCP-firmware-master/product/morello/scp_ramfw_fvp/ |
| A D | config_morello_pll.c | 27 .ref_rate = CLOCK_RATE_REFCLK,
37 .ref_rate = CLOCK_RATE_REFCLK,
47 .ref_rate = CLOCK_RATE_REFCLK,
57 .ref_rate = CLOCK_RATE_REFCLK,
67 .ref_rate = CLOCK_RATE_REFCLK,
77 .ref_rate = CLOCK_RATE_REFCLK,
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| /SCP-firmware-master/product/morello/module/morello_pll/include/ |
| A D | mod_morello_pll.h | 58 const uint64_t ref_rate; member
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| /SCP-firmware-master/product/n1sdp/module/n1sdp_pll/include/ |
| A D | mod_n1sdp_pll.h | 58 const uint64_t ref_rate; member
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| /SCP-firmware-master/product/morello/module/morello_pll/src/ |
| A D | mod_morello_pll.c | 90 if ((rate % config->ref_rate) == 0) { in pll_set_rate()
91 fbdiv_d = rate / config->ref_rate; in pll_set_rate()
111 if (((float)config->ref_rate / (float)refdiv) < in pll_set_rate()
117 (float)config->ref_rate; in pll_set_rate()
131 (((float)config->ref_rate / (float)refdiv) * in pll_set_rate()
359 (ctx->config->control_reg1 == NULL) || (ctx->config->ref_rate == 0)) { in morello_pll_element_init()
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| /SCP-firmware-master/product/n1sdp/module/n1sdp_pll/src/ |
| A D | mod_n1sdp_pll.c | 87 fbdiv = rate / config->ref_rate; in pll_set_rate()
99 ((float)rate * postdiv_iter * refdiv_iter) / config->ref_rate; in pll_set_rate()
111 fvco = (config->ref_rate * fbdiv_abs) / refdiv_iter; in pll_set_rate()
334 (ctx->config->control_reg1 == NULL) || (ctx->config->ref_rate == 0)) { in n1sdp_pll_element_init()
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