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Searched refs:ARM_AP_TZC_DRAM1_BASE (Results 1 – 7 of 7) sorted by relevance

/arm-trusted-firmware-2.8.0/include/plat/arm/common/
A Darm_def.h163 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ macro
172 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
585 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE
586 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
669 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
678 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
682 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
684 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
699 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
701 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE
[all …]
A Darm_pas_def.h69 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE)
A Dplat_arm.h44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
56 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
68 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
/arm-trusted-firmware-2.8.0/plat/arm/css/sgi/include/
A Dsgi_dmc620_tzc_regions.h15 .region_base = ARM_AP_TZC_DRAM1_BASE, \
30 .region_base = ARM_AP_TZC_DRAM1_BASE, \
/arm-trusted-firmware-2.8.0/plat/arm/board/juno/
A Djuno_tzmp1_def.h16 #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
18 #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1)
A Djuno_security.c41 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},
/arm-trusted-firmware-2.8.0/plat/arm/board/tc/include/
A Dplatform_def.h32 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \

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