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Searched refs:CPG_BASE (Results 1 – 8 of 8) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/renesas/common/include/registers/
A Dcpg_registers.h11 #define CPG_BASE (0xE6150000U) macro
14 #define CPG_SMSTPCR2 (CPG_BASE + 0x0138U)
16 #define CPG_SRCR2 (CPG_BASE + 0x00B0U)
18 #define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
20 #define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
22 #define CPG_CPGWPR (CPG_BASE + 0x0900U)
24 #define CPG_CPGWPCR (CPG_BASE + 0x0904U)
37 #define SCMSTPCR0 (CPG_BASE + 0x0B20U)
39 #define SCMSTPCR1 (CPG_BASE + 0x0B24U)
41 #define SCMSTPCR2 (CPG_BASE + 0x0B28U)
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_b/
A Dboot_init_dram_regdef.h37 #define CPG_FRQCRB (CPG_BASE + 0x0004U)
39 #define CPG_PLLECR (CPG_BASE + 0x00D0U)
40 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
41 #define CPG_SRCR4 (CPG_BASE + 0x00BCU)
42 #define CPG_PLL3CR (CPG_BASE + 0x00DCU)
43 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
44 #define CPG_FRQCRD (CPG_BASE + 0x00E4U)
45 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
46 #define CPG_CPGWPR (CPG_BASE + 0x0900U)
47 #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
/arm-trusted-firmware-2.8.0/drivers/renesas/common/
A Dddr_regs.h245 #define CPG_BASE 0xE6150000U macro
246 #define CPG_FRQCRB (CPG_BASE + 0x0004U)
247 #define CPG_PLLECR (CPG_BASE + 0x00D0U)
248 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
249 #define CPG_SRCR4 (CPG_BASE + 0x00BCU)
250 #define CPG_PLL3CR (CPG_BASE + 0x00DCU)
251 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
252 #define CPG_FRQCRD (CPG_BASE + 0x00E4U)
253 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
254 #define CPG_CPGWPR (CPG_BASE + 0x0900U)
[all …]
/arm-trusted-firmware-2.8.0/plat/renesas/common/include/
A Drcar_def.h225 #define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
226 #define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
228 #define CPG_PLL0CR (CPG_BASE + 0x00D8U)
229 #define CPG_PLL2CR (CPG_BASE + 0x002CU)
230 #define CPG_PLL4CR (CPG_BASE + 0x01F4U)
231 #define CPG_CPGWPCR (CPG_BASE + 0x0904U)
/arm-trusted-firmware-2.8.0/drivers/renesas/common/scif/
A Dscif.S25 #define CPG_BASE (0xE6150000) macro
172 ldr x0, =CPG_BASE
/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/V3M/
A Dpfc_init_v3m.c452 #define CPG_BASE (0xE6150000U) macro
453 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
454 #define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/M3/
A Dpfc_init_m3.c581 #define CPG_BASE (0xE6150000U) macro
582 #define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
583 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
/arm-trusted-firmware-2.8.0/drivers/renesas/rzg/pfc/G2M/
A Dpfc_init_g2m.c581 #define CPG_BASE (0xE6150000U) macro
582 #define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)
583 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)

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