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Searched refs:CPU1 (Results 1 – 8 of 8) sorted by relevance

/arm-trusted-firmware-2.8.0/fdts/
A Dmorello-fvp.dts38 cpu = <&CPU1>;
57 CPU1: cpu1@100 { label
A Dtc.dts33 cpu = <&CPU1>;
118 CPU1:cpu@100 { label
530 cpu = <&CPU1>;
A Dfvp-defs.dtsi77 #define CPU_1 CPU(1, c1, p1) /* CPU1: 0.1; 1.0 */
/arm-trusted-firmware-2.8.0/plat/arm/board/tc/fdts/
A Dtc_spmc_manifest.dts112 CPU1:cpu@100 { label
A Dtc_spmc_optee_sp_manifest.dts111 CPU1:cpu@100 { label
/arm-trusted-firmware-2.8.0/plat/marvell/armada/a8k/common/
A Dplat_pm.c69 CPU1, enumerator
204 if (plat_marvell_cpu_powerdown(CPU1) == -1) in plat_marvell_early_cpu_powerdown()
/arm-trusted-firmware-2.8.0/docs/design/
A Dpsci-pd-tree.rst250 CPU1 | 3 | |
A Dfirmware-design.rst2159 CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2160 disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2215 | Lock_0 | for CPU1
2218 | Lock_1 | for CPU1
2223 | Lock_N | for CPU1
2232 operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1

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