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Searched refs:CTL_REG (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/
A Ddfs.c503 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
513 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
521 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
537 mmio_write_32(CTL_REG(i, 27), in gen_rk3399_ctl_params_f0()
559 mmio_write_32(CTL_REG(i, 48), in gen_rk3399_ctl_params_f0()
568 mmio_write_32(CTL_REG(i, 56), in gen_rk3399_ctl_params_f0()
577 mmio_write_32(CTL_REG(i, 63), in gen_rk3399_ctl_params_f0()
594 mmio_write_32(CTL_REG(i, 124), in gen_rk3399_ctl_params_f0()
606 mmio_write_32(CTL_REG(i, 147), in gen_rk3399_ctl_params_f0()
809 mmio_write_32(CTL_REG(i, 49), in gen_rk3399_ctl_params_f1()
[all …]
A Dsuspend.c181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
476 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); in dram_all_config()
501 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)&params_ctl[1], in pctl_cfg()
503 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); in pctl_cfg()
518 mmio_setbits_32(CTL_REG(ch, 0), START); in pctl_cfg()
593 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
594 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
613 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { in pctl_start()
622 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
632 while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) { in pctl_start()
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/include/shared/
A Daddressmap_shared.h92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) macro

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