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Searched refs:DDRC_PCTRL_0 (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dddr4_dvfs.c153 mmio_write_32(DDRC_PCTRL_0(0), 0x0); in ddr4_swffc()
224 mmio_write_32(DDRC_PCTRL_0(0), 0x1); in ddr4_swffc()
A Ddram_retention.c36 mmio_write_32(DDRC_PCTRL_0(0), 0x0); in dram_enter_retention()
193 mmio_write_32(DDRC_PCTRL_0(0), 0x1); in dram_exit_retention()
A Dlpddr4_dvfs.c77 mmio_write_32(DDRC_PCTRL_0(0), 0x0); in lpddr4_swffc()
289 mmio_write_32(DDRC_PCTRL_0(0), 0x1); in lpddr4_swffc()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h185 #define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) macro

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