Searched refs:SOCFPGA_SYSMGR (Results 1 – 10 of 10) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/intel/soc/common/soc/ |
| A D | socfpga_emac.c | 21 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), in socfpga_emac_init()
23 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), in socfpga_emac_init()
25 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), in socfpga_emac_init()
28 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), in socfpga_emac_init()
|
| A D | socfpga_reset_manager.c | 193 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), in socfpga_bridges_enable()
200 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), in socfpga_bridges_enable()
252 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), in socfpga_bridges_disable()
255 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
257 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), in socfpga_bridges_disable()
264 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS), in socfpga_bridges_disable()
273 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0); in socfpga_bridges_disable()
|
| A D | socfpga_firewall.c | 98 mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3)); in enable_ns_peripheral_access()
|
| /arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/soc/ |
| A D | agilex_mmc.c | 15 mmio_write_32(SOCFPGA_SYSMGR(SDMMC), in agx_mmc_init()
|
| A D | agilex_pinmux.c | 191 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8); in config_fpgaintf_mod()
|
| A D | agilex_clock_manager.c | 272 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), in config_clkmgr_handoff()
274 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), in config_clkmgr_handoff()
286 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); in get_ref_clk()
293 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); in get_ref_clk()
|
| /arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/soc/ |
| A D | s10_mmc.c | 15 mmio_write_32(SOCFPGA_SYSMGR(SDMMC), in s10_mmc_init()
|
| A D | s10_clock_manager.c | 193 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), in config_clkmgr_handoff()
195 mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), in config_clkmgr_handoff()
208 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); in get_ref_clk()
215 scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); in get_ref_clk()
|
| /arm-trusted-firmware-2.8.0/plat/intel/soc/common/sip/ |
| A D | socfpga_sip_ecc.c | 36 dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); in cold_reset_for_ecc_dbe()
|
| /arm-trusted-firmware-2.8.0/plat/intel/soc/common/include/ |
| A D | socfpga_system_manager.h | 51 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ macro
|
Completed in 7 milliseconds