Home
last modified time | relevance | path

Searched refs:U (Results 1 – 25 of 929) sorted by relevance

12345678910>>...38

/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t194/
A Dtegra_def.h15 #define BL31_SIZE U(0x40000)
20 #define PLATFORM_CLUSTER_COUNT U(4)
34 #define PSTATE_ID_CORE_IDLE U(6)
36 #define PSTATE_ID_SOC_POWERDN U(2)
44 #define PLAT_MAX_RET_STATE U(1)
45 #define PLAT_MAX_OFF_STATE U(8)
59 #define TEGRA194_CLK_SE U(124)
69 #define BOARD_MASK_BITS U(0xFF)
70 #define BOARD_SHIFT_BITS U(24)
71 #define MISCREG_PFCFG U(0x200C)
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t186/
A Dtegra_def.h16 #define BL31_SIZE U(0x40000)
37 #define MCE_ARI_APERTURES_MAX U(6)
45 #define MCE_CORE_ID_MAX U(8)
46 #define MCE_CORE_ID_MASK U(0x7)
53 #define PSTATE_ID_CORE_IDLE U(6)
55 #define PSTATE_ID_SOC_POWERDN U(2)
63 #define PLAT_MAX_RET_STATE U(1)
64 #define PLAT_MAX_OFF_STATE U(8)
83 #define TEGRA186_CLK_SE U(103)
92 #define MISCREG_PFCFG U(0x200C)
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t210/
A Dtegra_def.h16 #define BL31_SIZE U(0x40000)
21 #define PSTATE_ID_CORE_POWERDN U(7)
22 #define PSTATE_ID_CLUSTER_IDLE U(16)
23 #define PSTATE_ID_SOC_POWERDN U(27)
37 #define PLAT_MAX_RET_STATE U(1)
79 #define MSELECT_CONFIG U(0x0)
80 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
81 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
82 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
83 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/drivers/include/
A Dt194_nvg.h25 TEGRA_NVG_VERSION_MINOR = U(7)
118 TEGRA_NVG_CORE_C0 = U(0),
119 TEGRA_NVG_CORE_C1 = U(1),
120 TEGRA_NVG_CORE_C6 = U(6),
121 TEGRA_NVG_CORE_C7 = U(7),
127 TEGRA_NVG_REBOOT = U(1)
137 TEGRA_NVG_CG_CG0 = U(0),
138 TEGRA_NVG_CG_CG7 = U(7)
234 uint32_t vfiq : U(1);
236 uint32_t fiq : U(1);
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046ardb/
A Dddr_init.c21 .cs[0].bnds = U(0x1FF),
23 .cs[1].bnds = U(0x1FF),
58 .cdr[1] = U(0xC1),
66 .cs[0].bnds = U(0x1FF),
103 .cdr[1] = U(0xC1),
152 .cdr[1] = U(0xC1),
193 {U(1600), U(8), U(7)},
194 {U(1867), U(8), U(7)},
195 {U(2134), U(8), U(9)},
200 {U(0x04), rce, U(0x01020304), U(0x06070805)},
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160aqds/
A Dddr_init.c27 .cs[0].bnds = U(0x03FF),
28 .cs[1].bnds = U(0x03FF),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
62 .md_cntl = U(0x00),
65 .init_addr = U(0x00),
113 .md_cntl = U(0x00),
180 .rdimm = U(0),
183 .n_ranks = U(2),
207 .n_ranks = U(2),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2162aqds/
A Dddr_init.c27 .cs[0].bnds = U(0x03FFU),
28 .cs[1].bnds = U(0x03FF),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
62 .md_cntl = U(0x00),
65 .init_addr = U(0x00),
113 .md_cntl = U(0x00),
164 .md_cntl = U(0x00),
180 .rdimm = 0U,
[all …]
/arm-trusted-firmware-2.8.0/include/drivers/arm/
A Dtzc380.h14 #define ACTION_OFF U(0x004)
15 #define LOCKDOWN_RANGE_OFF U(0x008)
17 #define INT_STATUS U(0x010)
18 #define INT_CLEAR U(0x014)
22 #define FAIL_CONTROL_OFF U(0x028)
23 #define FAIL_ID U(0x02c)
38 #define ACTION_RV_MASK U(0x3)
39 #define ACTION_RV_LOWOK U(0x0)
40 #define ACTION_RV_LOWERR U(0x1)
41 #define ACTION_RV_HIGHOK U(0x2)
[all …]
A Dgic600ae_fmu.h21 #define GICFMU_KEY U(0xEA0)
43 #define FMU_BLK_GICD U(0)
46 #define FMU_BLK_ITS0 U(4)
47 #define FMU_BLK_ITS1 U(5)
48 #define FMU_BLK_ITS2 U(6)
49 #define FMU_BLK_ITS3 U(7)
50 #define FMU_BLK_ITS4 U(8)
51 #define FMU_BLK_ITS5 U(9)
52 #define FMU_BLK_ITS6 U(10)
53 #define FMU_BLK_ITS7 U(11)
[all …]
A Dtzc_dmc500.h13 #define SI_STATUS_OFFSET U(0x000)
22 #define SI_FAIL_ID_OFFSET U(0x014)
23 #define SI_INT_CLR_OFFSET U(0x04c)
29 #define SI0_BASE U(0x0000)
30 #define SI1_BASE U(0x0200)
35 #define SI_EMPTY_MASK U(0x01)
58 #define DIRECTION_MASK U(0x1)
59 #define NON_SECURE_MASK U(0x1)
60 #define PRIVILEGED_MASK U(0x1)
88 #define PMU_REQ_INT_EN U(0x1)
[all …]
A Dcci.h36 #define CTRL_OVERRIDE_REG U(0x0)
37 #define SECURE_ACCESS_REG U(0x8)
38 #define STATUS_REG U(0xc)
44 #define PERIPHERAL_ID0 U(0xFE0)
53 #define COMPONENT_ID0 U(0xFF0)
54 #define COMPONENT_ID1 U(0xFF4)
55 #define COMPONENT_ID2 U(0xFF8)
56 #define COMPONENT_ID3 U(0xFFC)
63 #define SNOOP_CTRL_REG U(0x0)
64 #define SH_OVERRIDE_REG U(0x4)
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/include/
A Dplatform_def.h18 #define PLAT_PRIMARY_CPU U(0x0)
30 #define PLAT_MAX_PWR_LVL U(2)
31 #define PLAT_MAX_OFF_STATE U(4)
37 #define PLAT_PRI_BITS U(3)
43 #define BL2_BASE U(0x920000)
46 #define BL31_BASE U(0x900000)
129 #define WDOG_WSR U(0x2)
139 #define SRC_A53RCR0 U(0x4)
140 #define SRC_A53RCR1 U(0x8)
147 #define SNVS_LPCR U(0x38)
[all …]
/arm-trusted-firmware-2.8.0/include/export/common/tbbr/
A Dtbbr_img_def_exp.h15 #define FIP_IMAGE_ID U(0)
18 #define BL2_IMAGE_ID U(1)
21 #define SCP_BL2_IMAGE_ID U(2)
24 #define BL31_IMAGE_ID U(3)
27 #define BL32_IMAGE_ID U(4)
30 #define BL33_IMAGE_ID U(5)
50 #define FWU_CERT_ID U(17)
68 #define HW_CONFIG_ID U(23)
83 #define GPT_IMAGE_ID U(28)
89 #define ENC_IMAGE_ID U(30)
[all …]
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_def.h237 #define GPIO_BANK_A U(0)
238 #define GPIO_BANK_B U(1)
239 #define GPIO_BANK_C U(2)
240 #define GPIO_BANK_D U(3)
241 #define GPIO_BANK_E U(4)
242 #define GPIO_BANK_F U(5)
243 #define GPIO_BANK_G U(6)
244 #define GPIO_BANK_H U(7)
245 #define GPIO_BANK_I U(8)
247 #define GPIO_BANK_J U(9)
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/drivers/se/
A Dse_private.h15 #define SE0_SECURITY U(0x18)
19 #define SE0_SHA_GSCID_0 U(0x100)
22 #define SE0_SHA_CONFIG U(0x104)
33 #define SE0_CONFIG_DST_SHIFT U(2)
43 #define SE0_IN_ADDR U(0x10c)
67 #define SE0_OPERATION_SHIFT U(0)
83 #define SE0_SHA_STATUS_IDLE U(0)
94 #define SE0_INT_ENABLE U(0x88)
98 #define SE0_INT_STATUS U(0x8C)
129 #define OP_MASK_BITS U(0x7)
[all …]
/arm-trusted-firmware-2.8.0/include/arch/aarch32/
A Darch.h18 #define MIDR_VAR_BITS U(4)
20 #define MIDR_REV_BITS U(4)
156 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
157 (U(1) << 3))
196 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
197 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
198 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
258 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
305 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
383 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
[all …]
/arm-trusted-firmware-2.8.0/plat/renesas/common/include/
A Drcar_def.h19 #define FLASH0_BASE U(0x08000000)
20 #define FLASH0_SIZE U(0x04000000)
32 #define DRAM1_BASE U(0x40000000)
33 #define DRAM1_SIZE U(0x80000000)
105 #define ARM_IRQ_SEC_SGI_0 U(8)
106 #define ARM_IRQ_SEC_SGI_1 U(9)
107 #define ARM_IRQ_SEC_SGI_2 U(10)
108 #define ARM_IRQ_SEC_SGI_3 U(11)
113 #define ARM_IRQ_SEC_RPC U(70)
161 #define RCAR_MAJOR_SHIFT U(4)
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mq/include/
A Dplatform_def.h13 #define PLAT_PRIMARY_CPU U(0x0)
25 #define PLAT_MAX_PWR_LVL U(2)
26 #define PLAT_MAX_OFF_STATE U(4)
27 #define PLAT_MAX_RET_STATE U(1)
33 #define BL31_BASE U(0x910000)
34 #define BL31_LIMIT U(0x920000)
93 #define GPV_SIZE U(0x800000)
97 #define WDOG_WSR U(0x2)
107 #define SRC_A53RCR0 U(0x4)
108 #define SRC_A53RCR1 U(0x8)
[all …]
/arm-trusted-firmware-2.8.0/include/lib/el3_runtime/aarch64/
A Dcontext.h17 #define CTX_GPREG_X0 U(0x0)
18 #define CTX_GPREG_X1 U(0x8)
19 #define CTX_GPREG_X2 U(0x10)
20 #define CTX_GPREG_X3 U(0x18)
21 #define CTX_GPREG_X4 U(0x20)
22 #define CTX_GPREG_X5 U(0x28)
23 #define CTX_GPREG_X6 U(0x30)
24 #define CTX_GPREG_X7 U(0x38)
25 #define CTX_GPREG_X8 U(0x40)
26 #define CTX_GPREG_X9 U(0x48)
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/include/
A Dplatform_def.h20 #define PLAT_PRIMARY_CPU U(0x0)
32 #define PLAT_MAX_PWR_LVL U(2)
40 #define BL2_BASE U(0x970000)
43 #define BL31_BASE U(0x950000)
59 #define PLAT_PRI_BITS U(3)
137 #define RSTn_CSR U(0x0)
138 #define CLK_EN_CSR U(0x4)
139 #define RST_DIV U(0x8)
143 #define WDOG_WSR U(0x2)
159 #define SNVS_LPCR U(0x38)
[all …]
/arm-trusted-firmware-2.8.0/include/drivers/nxp/sfp/
A Dfuse_prov.h15 #define ERROR_WRITE U(0xA)
19 #define FLAG_POVDD_SHIFT U(0)
20 #define FLAG_SYSCFG_SHIFT U(1)
21 #define FLAG_SRKH_SHIFT U(2)
22 #define FLAG_MC_SHIFT U(3)
23 #define FLAG_DCV0_SHIFT U(4)
24 #define FLAG_DCV1_SHIFT U(5)
25 #define FLAG_DRV0_SHIFT U(6)
49 #define SCB_WP_SHIFT U(0)
52 #define SCB_ZD_SHIFT U(5)
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/drivers/
A Dpmc.h17 #define PMC_CONFIG U(0x0)
18 #define PMC_IO_DPD_SAMPLE U(0x20)
19 #define PMC_DPD_ENABLE_0 U(0x24)
22 #define PMC_SCRATCH1 U(0x54)
23 #define PMC_CRYPTO_OP_0 U(0xf4)
25 #define PMC_SCRATCH31 U(0x118)
26 #define PMC_SCRATCH32 U(0x11C)
27 #define PMC_SCRATCH33 U(0x120)
28 #define PMC_SCRATCH39 U(0x138)
29 #define PMC_SCRATCH40 U(0x13C)
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ls1028ardb/
A Dddr_init.c17 .cs[0].bnds = U(0xFF),
24 .timing_cfg[4] = U(0x2),
45 .cdr[1] = U(0xA181),
51 .dq_map[2] = U(0),
97 .n_ranks = U(1),
102 .rdimm = U(0),
103 .mirrored_dimm = U(0),
104 .n_row_addr = U(16),
105 .n_col_addr = U(10),
107 .edc_config = U(2),
[all …]
/arm-trusted-firmware-2.8.0/include/arch/aarch64/
A Darch.h19 #define MIDR_VAR_BITS U(4)
397 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
398 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
399 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
405 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
406 (U(1) << 4) | (U(1) << 3))
408 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
409 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
410 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
498 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
[all …]
/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32_gpio.h12 #define GPIO_MODE_OFFSET U(0x00)
13 #define GPIO_TYPE_OFFSET U(0x04)
14 #define GPIO_SPEED_OFFSET U(0x08)
15 #define GPIO_PUPD_OFFSET U(0x0C)
16 #define GPIO_OD_OFFSET U(0x14)
17 #define GPIO_BSRR_OFFSET U(0x18)
18 #define GPIO_AFRL_OFFSET U(0x20)
19 #define GPIO_AFRH_OFFSET U(0x24)
24 #define GPIO_PIN_(_x) U(_x)
46 #define GPIO_NO_PULL U(0x00)
[all …]

Completed in 61 milliseconds

12345678910>>...38