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Searched refs:cmpcr_off (Results 1 – 1 of 1) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_syscfg.c120 static void enable_io_comp_cell_finish(uintptr_t cmpcr_off) in enable_io_comp_cell_finish() argument
126 while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) { in enable_io_comp_cell_finish()
134 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL); in enable_io_comp_cell_finish()
137 static void disable_io_comp_cell(uintptr_t cmpcr_off) in disable_io_comp_cell() argument
141 if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) || in disable_io_comp_cell()
142 ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) & in disable_io_comp_cell()
147 value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT; in disable_io_comp_cell()
149 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); in disable_io_comp_cell()
152 value |= mmio_read_32(SYSCFG_BASE + cmpcr_off); in disable_io_comp_cell()
154 mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL); in disable_io_comp_cell()
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