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Searched refs:debug (Results 1 – 25 of 64) sorted by relevance

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/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/phy-gen1/
A Dphy.c25 debug("clk_cntl = 0x%x\n", regs->clk_cntl); in cal_ddr_sdram_clk_cntl()
33 debug("cdr[0] = 0x%x\n", regs->cdr[0]); in cal_ddr_cdr()
34 debug("cdr[1] = 0x%x\n", regs->cdr[1]); in cal_ddr_cdr()
73 regs->debug[2] = U(0x00000400); in cal_ddr_dbg()
74 regs->debug[4] = U(0xff800800); in cal_ddr_dbg()
75 regs->debug[5] = U(0x08000800); in cal_ddr_dbg()
76 regs->debug[6] = U(0x08000800); in cal_ddr_dbg()
77 regs->debug[7] = U(0x08000800); in cal_ddr_dbg()
78 regs->debug[8] = U(0x08000800); in cal_ddr_dbg()
81 regs->debug[28] = popts->cpo_sample; in cal_ddr_dbg()
[all …]
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A Ddimm.c167 debug("n_ranks %d\n", pdimm->n_ranks); in cal_dimm_params()
251 debug("rdimm %d\n", pdimm->rdimm); in cal_dimm_params()
253 debug("rc 0x%x\n", pdimm->rc); in cal_dimm_params()
321 debug("taa_ps %d\n", pdimm->taa_ps); in cal_dimm_params()
327 debug("trcd_ps %d\n", pdimm->trcd_ps); in cal_dimm_params()
333 debug("trp_ps %d\n", pdimm->trp_ps); in cal_dimm_params()
338 debug("tras_ps %d\n", pdimm->tras_ps); in cal_dimm_params()
343 debug("trc_ps %d\n", pdimm->trc_ps); in cal_dimm_params()
347 debug("trfc1_ps %d\n", pdimm->trfc1_ps); in cal_dimm_params()
357 debug("tfaw_ps %d\n", pdimm->tfaw_ps); in cal_dimm_params()
[all …]
A Dddr.c302 debug("cs %d\n", i); in cal_odt()
304 debug(" odt_rd_cfg 0x%x\n", in cal_odt()
307 debug(" odt_wr_cfg 0x%x\n", in cal_odt()
313 debug(" odt_rtt_wr 0x%x\n", in cal_odt()
534 debug("Controller %d\n", i); in parse_spd()
536 debug("DIMM %d\n", j); in parse_spd()
545 debug("addr 0x%x\n", addr); in parse_spd()
619 debug("cal cs\n"); in parse_spd()
701 debug("CS %d\n", i); in assign_intlv_addr()
762 debug("CS %d\n", i); in assign_non_intlv_addr()
[all …]
A Dddrc.c326 if (regs->debug[i] != 0) { in ddrc_set_regs()
332 ddr_out32(&ddr->debug[i], regs->debug[i]); in ddrc_set_regs()
363 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
368 if (regs->debug[28] != 0) { in ddrc_set_regs()
370 tmp |= regs->debug[28] & 0xff; in ddrc_set_regs()
374 ddr_out32(&ddr->debug[28], tmp); in ddrc_set_regs()
380 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
561 tmp = ddr_in32(&ddr->debug[13]); in ddrc_set_regs()
567 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
568 debug("debug[28] 0x%x\n", tmp); in ddrc_set_regs()
[all …]
A Dregs.c69 debug("cs%d\n", i); in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
321 debug("PAR_LAT = 0x%x\n", par_lat); in cal_timing_cfg()
519 debug("interval = 0x%x\n", regs->interval); in cal_ddr_sdram_interval()
845 debug("dq_map[0] = 0x%x\n", regs->dq_map[0]); in cal_ddr_dq_mapping()
846 debug("dq_map[1] = 0x%x\n", regs->dq_map[1]); in cal_ddr_dq_mapping()
863 debug("zq_cntl = 0x%x\n", regs->zq_cntl); in cal_ddr_zq_cntl()
881 debug("eor = 0x%x\n", regs->eor); in cal_ddr_eor()
983 debug("cacheline size %d\n", cacheline); in cal_ddr_addr_dec()
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]); in cal_ddr_addr_dec()
[all …]
A Dutility.c120 debug("%s: nothing to do.\n", __func__); in disable_unused_ddrc()
138 debug("valid_spd_mask = 0x%x\n", valid_spd_mask); in disable_unused_ddrc()
149 debug("Disable first DDR controller\n"); in disable_unused_ddrc()
155 debug("Disable second DDR controller\n"); in disable_unused_ddrc()
165 debug("Both controllers in use.\n"); in disable_unused_ddrc()
187 debug("Setting HN-F node %d\n", i); in disable_unused_ddrc()
188 debug("nodeid = 0x%x\n", nodeid); in disable_unused_ddrc()
/arm-trusted-firmware-2.8.0/drivers/marvell/comphy/
A Dphy-comphy-common.h15 #define debug(format...) printf(format) macro
17 #define debug(format, arg...) macro
147 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set()
149 debug("old value = 0x%x ==> ", mmio_read_32(addr)); in reg_set()
152 debug("new val 0x%x\n", mmio_read_32(addr)); in reg_set()
159 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", in reg_set16()
161 debug("old value = 0x%x ==> ", mmio_read_16(addr)); in reg_set16()
164 debug("new val 0x%x\n", mmio_read_16(addr)); in reg_set16()
A Dphy-comphy-cp110.c410 debug("stage: Comphy configuration\n"); in mvebu_cp110_comphy_sata_power_on()
824 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_sgmii_power_on()
1236 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_xfi_power_on()
1329 debug("On lane %d\n", comphy_index); in mvebu_cp110_comphy_pcie_power_on()
1664 debug("stage: Comphy power up\n"); in mvebu_cp110_comphy_pcie_power_on()
1727 debug("stage: Check PLL\n"); in mvebu_cp110_comphy_pcie_power_on()
1924 debug("stage: RF Reset\n"); in mvebu_cp110_comphy_rxaui_power_on()
2062 debug("stage: Comphy power up\n"); in mvebu_cp110_comphy_usb3_power_on()
2069 debug("stage: Check PLL\n"); in mvebu_cp110_comphy_usb3_power_on()
2095 debug("rx_training preparation\n\n"); in rx_pre_train()
[all …]
/arm-trusted-firmware-2.8.0/docs/security_advisories/
A Dsecurity-advisory-tfv-2.rst5 | Title | Enabled secure self-hosted invasive debug interface can |
25 The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug
28 entrypoint code, which enables debug exceptions from the secure world. This can
31 by saving and restoring the appropriate debug registers), this may allow a
34 The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions
42 secure self-hosted invasive debug enablement. TF assigns these bits to ``00``
43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
48 However, given that TF contains no support for handling debug exceptions, the
49 ``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046aqds/
A Dddr_init.c34 debug("RDIMM parameters not set.\n"); in ddr_board_options()
69 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
70 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
71 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/phy-gen2/
A Dphy.c1887 debug("Initialize PHY %d config\n", i); in c_init_phy_config()
2047 debug("End of initialization\n"); in wait_fw_done()
2088 debug("/tDWL, MREP, MRD and MWD\n"); in wait_fw_done()
2092 debug("End of CA training\n"); in wait_fw_done()
2104 debug("Timed out\n"); in wait_fw_done()
2560 debug("Initializing message block\n"); in compute_ddr_phy()
2597 debug("Load 1D firmware\n"); in compute_ddr_phy()
2606 debug("Execute firmware\n"); in compute_ddr_phy()
2627 debug("Load 2D firmware\n"); in compute_ddr_phy()
2636 debug("Execute 2D firmware\n"); in compute_ddr_phy()
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ls1088aqds/
A Dddr_init.c37 debug("RDIMM parameters not set.\n"); in ddr_board_options()
66 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
67 debug("DDR PLL %lu\n", sys.freq_ddr_pll0); in init_ddr()
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ls1088ardb/
A Dddr_init.c38 debug("RDIMM parameters not set.\n"); in ddr_board_options()
67 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
68 debug("DDR PLL %lu\n", sys.freq_ddr_pll0); in init_ddr()
/arm-trusted-firmware-2.8.0/drivers/marvell/secure_dfx_access/
A Dmisc_dfx.c17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
108 debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val); in mvebu_dfx_misc_handle()
A Darmada_thermal.c17 #define debug(format...) NOTICE(format) macro
19 #define debug(format, arg...) macro
212 debug("thermal: Initialization done\n"); in armada_ap806_thermal_init()
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ls1043ardb/
A Dddr_init.c50 .debug[28] = U(0x00700046),
143 debug("platform clock %lu\n", sys.freq_platform);
144 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
145 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
/arm-trusted-firmware-2.8.0/include/drivers/nxp/ddr/
A Dddr.h36 #define debug(...) INFO(__VA_ARGS__) macro
38 #define debug(...) VERBOSE(__VA_ARGS__) macro
75 unsigned int debug[64]; member
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046afrwy/
A Dddr_init.c156 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
157 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
158 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/arm-trusted-firmware-2.8.0/plat/marvell/armada/common/
A Dmrvl_sip_svc.c25 #define debug(format...) NOTICE(format) macro
27 #define debug(format, arg...) macro
85 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n", in mrvl_sip_smc_handler()
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ls1028ardb/
A Dddr_init.c53 .debug[28] = U(0x00700046),
169 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
170 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/
A Dtegra_common.mk42 ${TEGRA_LIBS}/debug/profiler.c \
44 ${TEGRA_LIBS}/debug/profiler.c \
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160ardb/
A Dddr_init.c177 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
178 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
179 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046ardb/
A Dddr_init.c210 debug("RDIMM parameters not set.\n"); in ddr_board_options()
245 debug("platform clock %lu\n", sys.freq_platform); in init_ddr()
246 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); in init_ddr()
247 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); in init_ddr()
/arm-trusted-firmware-2.8.0/plat/mediatek/build_helpers/
A Dconditional_eval_options.mk22 ifeq ($(BUILD_TYPE),debug)
/arm-trusted-firmware-2.8.0/docs/plat/
A Dwarp7.rst80 …ot/u-boot.cfgout -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
90 tools/cert_create/cert_create -n --rot-key "build/warp7/debug/rot_key.pem" \
94 --tb-fw=build/warp7/debug/bl2.bin \
176 …oot.cfgout.warp7 -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.…
179 cp build/warp7/debug/bl2.bin.imx ${TEMP}

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