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/arm-trusted-firmware-2.8.0/plat/common/
A Dplat_log_common.c18 unsigned int level; in plat_log_get_prefix() local
21 level = LOG_LEVEL_ERROR; in plat_log_get_prefix()
23 level = LOG_LEVEL_VERBOSE; in plat_log_get_prefix()
25 level = log_level; in plat_log_get_prefix()
28 return plat_prefix_str[(level / 10U) - 1U]; in plat_log_get_prefix()
/arm-trusted-firmware-2.8.0/plat/mediatek/lib/mtk_init/
A Dmtk_init.c19 void mtk_init_one_level(uint32_t level) in mtk_init_one_level() argument
24 if (level >= MTK_INIT_LVL_MAX) { in mtk_init_one_level()
25 ERROR("invalid level:%u\n", level); in mtk_init_one_level()
29 INFO("init calling level:%u\n", level); in mtk_init_one_level()
30 for (entry = initcall_list[level]; in mtk_init_one_level()
31 (entry != NULL) && (entry < initcall_list[level + 1]); in mtk_init_one_level()
/arm-trusted-firmware-2.8.0/lib/xlat_tables_v2/
A Dxlat_tables_utils.c141 unsigned int level) in xlat_tables_print_internal() argument
166 level_spacers[level], in xlat_tables_print_internal()
297 ++level) { in find_xlat_table_entry()
321 *out_level = level; in find_xlat_table_entry()
326 *out_level = level; in find_xlat_table_entry()
351 unsigned int level; in xlat_get_mem_attributes_internal() local
370 &level); in xlat_get_mem_attributes_internal()
385 *table_level = level; in xlat_get_mem_attributes_internal()
495 unsigned int level; in xlat_change_mem_attributes_ctx() local
501 &level); in xlat_change_mem_attributes_ctx()
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A Dxlat_tables_core.c307 if (level == 3U) { in xlat_tables_unmap_region_action()
342 assert(level < 3U); in xlat_tables_unmap_region_action()
363 assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX)); in xlat_tables_unmap_region()
401 level + 1U); in xlat_tables_unmap_region()
460 if (level == 3U) { in xlat_tables_map_region_action()
531 assert(level < 3U); in xlat_tables_map_region_action()
576 assert((level >= ctx->base_level) && (level <= XLAT_TABLE_LEVEL_MAX)); in xlat_tables_map_region()
604 table_idx_va, level); in xlat_tables_map_region()
610 level); in xlat_tables_map_region()
628 level + 1U); in xlat_tables_map_region()
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A Dxlat_tables_private.h84 unsigned long long addr_pa, unsigned int level);
/arm-trusted-firmware-2.8.0/include/lib/xlat_tables/
A Dxlat_tables_defs.h103 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ argument
104 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
106 #define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level)) argument
108 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1)) argument
110 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) argument
115 #define XLAT_TABLE_IDX(virtual_addr, level) \ argument
116 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
/arm-trusted-firmware-2.8.0/lib/xlat_tables/
A Dxlat_tables_common.c29 #define get_level_spacer(level) \ argument
30 (((level) == U(0)) ? LVL0_SPACER : \
31 (((level) == U(1)) ? LVL1_SPACER : \
190 unsigned int level) in mmap_desc() argument
327 unsigned int level) in init_xlation_table_inner() argument
329 assert((level >= XLAT_TABLE_LEVEL_MIN) && in init_xlation_table_inner()
330 (level <= XLAT_TABLE_LEVEL_MAX)); in init_xlation_table_inner()
359 } else if (level >= XLAT_BLOCK_LEVEL_MIN) { in init_xlation_table_inner()
372 level); in init_xlation_table_inner()
386 new_table, level + 1U); in init_xlation_table_inner()
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A Dxlat_tables_private.h38 unsigned int level, uintptr_t *max_va,
/arm-trusted-firmware-2.8.0/plat/marvell/armada/a3k/common/
A Da3700_ea.c26 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_ea_handler() local
63 if (level < MODE_EL3 && ea_reason == ERROR_EA_ASYNC && in plat_ea_handler()
68 syndrome, read_mpidr_el1(), get_el_str(level)); in plat_ea_handler()
/arm-trusted-firmware-2.8.0/lib/psci/
A Dpsci_setup.c45 unsigned char level) in psci_init_pwr_domain_node() argument
47 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()
50 psci_non_cpu_pd_nodes[node_idx].level = level; in psci_init_pwr_domain_node()
129 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree() local
140 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
159 (unsigned char)level); in populate_power_domain_tree()
167 level--; in populate_power_domain_tree()
170 if (level == (int) PSCI_CPU_PWR_LVL) in populate_power_domain_tree()
A Dpsci_common.c585 unsigned int level; in psci_acquire_pwr_domain_locks() local
588 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { in psci_acquire_pwr_domain_locks()
589 parent_idx = parent_nodes[level - 1U]; in psci_acquire_pwr_domain_locks()
603 unsigned int level; in psci_release_pwr_domain_locks() local
606 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { in psci_release_pwr_domain_locks()
607 parent_idx = parent_nodes[level - 1U]; in psci_release_pwr_domain_locks()
914 psci_non_cpu_pd_nodes[idx].level, in psci_print_power_domain_map()
/arm-trusted-firmware-2.8.0/plat/brcm/board/common/
A Dbcm_elog.c39 unsigned int level; member
98 int bcm_elog_init(void *base, uint32_t size, unsigned int level) in bcm_elog_init() argument
106 elog->level = level / 10; in bcm_elog_init()
196 unsigned int level = fmt[0]; in bcm_elog() local
198 if (!elog->is_active || level > elog->level) in bcm_elog()
201 prefix_str = plat_log_get_prefix(level); in bcm_elog()
/arm-trusted-firmware-2.8.0/plat/common/aarch64/
A Dplat_common.c90 unsigned int level = (unsigned int)GET_EL(read_spsr_el3()); in plat_default_ea_handler() local
94 read_mpidr_el1(), get_el_str(level)); in plat_default_ea_handler()
98 if (level != MODE_EL3) { in plat_default_ea_handler()
/arm-trusted-firmware-2.8.0/lib/xlat_tables/aarch32/
A Dnonlpae_tables.c293 unsigned int level) in mmap_desc() argument
297 switch (level) { in mmap_desc()
335 if (level == 2U) { in mmap_desc()
397 unsigned int level) in init_xlation_table_inner() argument
399 unsigned int level_size_shift = (level == 1U) ? in init_xlation_table_inner()
406 assert((level == 1U) || (level == 2U)); in init_xlation_table_inner()
420 if (level == 2U) { in init_xlation_table_inner()
421 printf(" 0x%lx %x " + 6 - 2 * level, in init_xlation_table_inner()
439 level); in init_xlation_table_inner()
474 level + 1); in init_xlation_table_inner()
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/arm-trusted-firmware-2.8.0/include/plat/brcm/common/
A Dbcm_elog.h15 int bcm_elog_init(void *base, uint32_t size, unsigned int level);
21 unsigned int level) in bcm_elog_init() argument
/arm-trusted-firmware-2.8.0/fdts/
A Da5ds.dts30 next-level-cache = <&L2>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
61 cache-level = <2>;
/arm-trusted-firmware-2.8.0/lib/zlib/
A Dzlib.h706 int level,
1246 int level));
1381 ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy));
1781 ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level,
1796 # define z_deflateInit(strm, level) \ argument
1797 deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))
1801 deflateInit2_((strm),(level),(method),(windowBits),(memLevel),\
1810 # define deflateInit(strm, level) \ argument
1811 deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream))
1814 # define deflateInit2(strm, level, method, windowBits, memLevel, strategy) \ argument
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/arm-trusted-firmware-2.8.0/docs/perf/
A Dpsci-performance-juno.rst85 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
117 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
136 There is no lock contention in TF generic code at power level 0 but the large
147 require locks at power level 0.
150 the cache associated with power level 0 is flushed (L1).
152 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
173 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
182 level 0, which only requires L1 cache flush.
184 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
221 2. Program wake up timer and suspend the lead CPU to the deepest power level.
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dimx8m_csu.h60 #define CSU_CSLx(i, level, lk) \ argument
61 {CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
/arm-trusted-firmware-2.8.0/docs/components/
A Dgranule-protection-tables-design.rst46 The GPT can function as either a 1 level or 2 level lookup depending on how a
47 PAS region is configured. The first step is the level 0 table, each entry in the
48 level 0 table controls access to a relatively large region in memory (block
50 mapping is used, or a level 0 entry can link to a level 1 table where relatively
64 which is how large each level 1 granule is, and L0GPTSZ (level 0 GPT size) which
65 determines how much physical memory is governed by each level 0 entry. A granule
119 the level 0 tables and ``gpt_init_pas_l1_tables`` takes an address and size for
120 building the level 1 tables which are linked from level 0 descriptors. The
122 its level 0 table in SRAM and its level 1 table(s) in DRAM.
145 #. Firmware must call ``gpt_init_l0_tables`` to initialize the level 0 tables to
A Dexception-handling.rst98 for more than one priority level.
107 A priority level is *active* when a handler at that priority level is currently
127 whilst a higher priority level is active, and would result in a panic.
129 level when a higher priority level is active.
143 top-level handler for interrupts that target EL3, as described in the
169 dispatcher may register more than one priority level.
211 priority level descriptors. Each entry in the array is of type
257 - The priority level for which the handler is being registered;
266 - There exists a descriptor with the priority level requested.
318 /* Install priority level descriptors for each dispatcher */
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A Dxlat-tables-lib-v2-design.rst17 translation regime than the exception level the library code is executing at;
90 - using a single level-2 translation table entry;
91 - using a level-2 intermediate entry to a level-3 translation table (which
97 page tables to refine the mappings. If a single level-2 entry has been used
98 here, a level-3 table will need to be allocated on the fly and the level-2
99 modified to point to this new level-3 table. This has a performance cost at
155 excluding the initial lookup level translation table, which is always
157 specify the number of level-2 and level-3 translation tables to pre-allocate
374 blocks of that level. For example, for a 4 KiB page size, a level 2 block entry
376 aligned to 2 MiB then additional level 3 tables are also needed.
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/arm-trusted-firmware-2.8.0/docs/getting_started/
A Dimage-terminology.rst22 - Previously, the format for 3rd level images had 2 forms; ``BL3`` was either
65 required to load and authenticate all 3rd level firmware images into their
82 abbreviation should be avoided; use the recommended **Other AP 3rd level
90 Other AP 3rd level images: ``AP_BL3_XXX``
93 The abbreviated names of the existing 3rd level images imply a load/execution
97 but new 3rd level images should be suffixed with an underscore followed by text
100 In systems where 3rd level images are provided by different vendors, the
132 SCP needs to load/authenticate multiple 3rd level images in future.
153 secure and normal world. The "level" of the BL image is relative to the world
184 underscore and the level of the firmware image.
/arm-trusted-firmware-2.8.0/plat/mediatek/common/lpm/
A Dmt_lp_rm.h21 int level; member
/arm-trusted-firmware-2.8.0/docs/design/
A Dpsci-pd-tree.rst26 over the sibling nodes at a particular level to find a specified power
28 a 'start' to an 'end' power level. The binary search is required to find the
29 node at each level. The natural way to perform this traversal is to
31 level.
58 highest power level implemented in the platform. This caters for platforms
60 the FVP has two cluster power domains at the highest level (1).
69 to consider at the next level. The sum of the values (number of children) of
70 all the entries at a level specifies the number of entries in the array for
71 the next level.
192 * Index of the first CPU power domain node level 0 which has this node
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