Home
last modified time | relevance | path

Searched refs:plat_params_from_bl2_t (Results 1 – 14 of 14) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/
A Dtegra_bl31_setup.c48 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
83 plat_params_from_bl2_t *bl31_get_plat_params(void) in bl31_get_plat_params()
96 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; in bl31_early_platform_setup2()
281 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in bl31_plat_arch_setup()
A Dtegra_pm.c156 const plat_params_from_bl2_t *plat_params; in tegra_pwr_domain_on_finish()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t210/
A Dplat_setup.c155 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup()
204 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_late_platform_setup()
281 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_supports_system_suspend()
A Dplat_psci_handlers.c47 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_validate_power_state()
347 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
435 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/
A Dtegra_private.h52 } plat_params_from_bl2_t; typedef
85 plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
127 plat_params_from_bl2_t *bl31_get_plat_params(void);
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/
A Dplat_setup.c189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in plat_early_platform_setup()
274 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
280 return (plat_params_from_bl2_t *)(uintptr_t)val; in plat_get_bl31_plat_params()
326 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params(); in plat_relocate_bl32_image()
A Dplat_psci_handlers.c106 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend()
283 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
376 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_private.h53 } plat_params_from_bl2_t; typedef
A Dhikey960_bl31_setup.c79 plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1; in bl31_early_platform_setup2()
A Dhikey960_bl2_setup.c35 static plat_params_from_bl2_t plat_params_from_bl2;
343 flush_dcache_range((uintptr_t)&plat_params_from_bl2, sizeof(plat_params_from_bl2_t)); in bl2_platform_setup()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/
A Dplat_secondary.c32 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_secondary_setup()
A Dplat_setup.c242 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_early_platform_setup()
385 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) in plat_get_bl31_plat_params()
394 return (plat_params_from_bl2_t *)(uintptr_t)val; in plat_get_bl31_plat_params()
A Dplat_psci_handlers.c118 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend()
267 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi()
346 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_on_finish()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/drivers/memctrl/
A Dmemctrl_v2.c123 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_mc_save_context()

Completed in 13 milliseconds