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Searched refs:r3 (Results 1 – 25 of 39) sorted by relevance

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/arm-trusted-firmware-2.8.0/drivers/st/uart/aarch32/
A Dstm32_console.S56 ands r3, r3, #USART_CR1_UE
67 bic r3, r3, #USART_CR1_UE
70 orr r3, r3, #(USART_CR1_TE | USART_CR1_FIFOEN)
73 bic r3, r3, #USART_CR2_STOP
77 add r3, r1, r3
78 udiv r3, r3, r2
84 add r3, r3, r1, lsl #1
85 udiv r3, r3, r2
88 bic r3, r3, #USART_BRR_DIV_FRACTION
89 orr r3, r3, r1
[all …]
/arm-trusted-firmware-2.8.0/drivers/imx/uart/
A Dimx_crash_uart.S36 movs r3, #0
37 str r3, [r4, #IMX_UART_CR2_OFFSET]
41 ldr r3, [r1, #0]
42 ands r3, #IMX_UART_CR2_SRST
46 movs r3, #IMX_UART_CR1_UARTEN
55 movw r3, #16423
63 movs r3, #132
71 mov r3, #32768
80 movw r3, #2626
82 movw r3, #2562
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S30 mov_imm r3, A5DS_HOLD_STATE_WAIT
31 str r3, [r2, r0]
105 mov r3, r0
112 lsleq r3, r0, #MPIDR_AFFINITY_BITS
115 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
116 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
117 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
120 mov r3, #A5DS_MAX_CPUS_PER_CLUSTER
121 mla r1, r2, r3, r1
122 mov r3, #A5DS_MAX_PE_PER_CPU
[all …]
/arm-trusted-firmware-2.8.0/lib/aarch32/
A Dmisc_helpers.S147 orr r3, r0, r1
148 tst r3, #0x3
249 1: ldr r3, [r1]
252 cmp r3, r6
256 cmp r3, r7
258 add r3, r3, r0
259 str r3, [r1]
288 ands r3, r3, #0xff
297 add r3, r0, r3 /* Diff(S) + r_offset */
298 ldr r4, [r3]
[all …]
A Dcache_helpers.S26 dcache_line_size r2, r3
28 sub r3, r2, #1
29 bic r0, r0, r3
86 ubfx r3, r2, \shift, \fw
87 lsl r3, r3, \ls
140 cmp r3, r1
194 mov r3, \level
195 sub r1, r3, #2
/arm-trusted-firmware-2.8.0/plat/arm/board/corstone700/common/
A Dcorstone700_helpers.S86 mov r3, r0
89 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
90 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
91 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
94 mov r3, #CORSTONE700_MAX_CPUS_PER_CLUSTER
95 mla r1, r2, r3, r1
96 mov r3, #CORSTONE700_MAX_PE_PER_CPU
97 mla r0, r1, r3, r0
/arm-trusted-firmware-2.8.0/drivers/ti/uart/aarch32/
A D16550_console.S57 ldr r3, [r0, #UARTLCR]
58 orr r3, r3, #UARTLCR_DLAB
63 and r3, r3, r2
67 mov r3, #3
68 str r3, [r0, #UARTLCR]
70 mov r3, #0
71 str r3, [r0, #UARTIER]
78 str r3, [r0, #UARTFCR]
80 mov r3, #3
81 str r3, [r0, #UARTMCR]
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S122 mov r3, r0
129 lsleq r3, r0, #MPIDR_AFFINITY_BITS
132 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
133 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
134 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
137 mov r3, #FVP_MAX_CPUS_PER_CLUSTER
138 mla r1, r2, r3, r1
139 mov r3, #FVP_MAX_PE_PER_CPU
140 mla r0, r1, r3, r0
/arm-trusted-firmware-2.8.0/drivers/arm/css/sds/aarch32/
A Dsds_helpers.S25 ubfx r3, r1, #0, #16
28 cmp r2, r3
38 mov r3, #0
49 add r3, r3, #0x1
50 cmp r1, r3
/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch32/
A Damu_helpers.S77 stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
79 stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
81 stcopr16 r2, r3, AMEVCNTR02 /* index 2 */
83 stcopr16 r2, r3, AMEVCNTR03 /* index 3 */
173 stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
175 stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
177 stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
179 stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
181 stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
183 stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
[all …]
/arm-trusted-firmware-2.8.0/lib/libc/aarch32/
A Dmemset.S38 mov r3, r1
49 stmiahs r12!, {r1, r3, r4, lr}
50 stmiahs r12!, {r1, r3, r4, lr}
54 stmiacs r12!, {r1, r3, r4, lr} /* write 16 bytes */
56 stmiami r12!, {r1, r3} /* write 8 bytes */
66 stmiacs r12!, {r1, r3} /* write 8 bytes */
/arm-trusted-firmware-2.8.0/plat/imx/imx7/common/
A Dimx7_helpers.S56 mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE
57 ldr r3, [r3, #0]
58 blx r3
/arm-trusted-firmware-2.8.0/drivers/arm/pl011/aarch32/
A Dpl011_console.S51 ldr r3, [r0, #UARTCR]
52 bic r3, r3, #PL011_UARTCR_UARTEN
53 str r3, [r0, #UARTCR]
58 push {r0,r3}
59 softudiv r0,r1,r2,r3
61 pop {r0,r3}
108 mov r4, r3
/arm-trusted-firmware-2.8.0/lib/compiler-rt/builtins/arm/
A Daeabi_ldivmod.S34 movs r1, r3
35 movs r3, r6
39 ldr r3, [sp, #12]
A Daeabi_uldivmod.S34 movs r1, r3
35 movs r3, r6
39 ldr r3, [sp, #12]
/arm-trusted-firmware-2.8.0/lib/xlat_tables_v2/aarch32/
A Denable_mmu.S26 mov r3, r0
61 tst r3, #DISABLE_DCACHE
83 mov r3, r0
113 tst r3, #DISABLE_DCACHE
/arm-trusted-firmware-2.8.0/plat/common/aarch32/
A Dcrash_console_helpers.S44 mov r3, lr
48 bx r3
/arm-trusted-firmware-2.8.0/bl32/sp_min/aarch32/
A Dentrypoint.S75 mov r12, r3
135 mov r3, r12
217 and r3, r0, #SCR_NS_BIT /* flags */
268 push {r2, r3}
270 pop {r0, r3}
287 ldcopr16 r2, r3, CNTPCT_64
288 strd r2, r3, [r0]
/arm-trusted-firmware-2.8.0/bl2/aarch32/
A Dbl2_el3_entrypoint.S20 mov r12, r3
37 mov r3, r12
A Dbl2_entrypoint.S35 mov r12, r3
120 mov r3, r12
/arm-trusted-firmware-2.8.0/common/aarch32/
A Ddebug.S121 mov r3, lr
129 bx r3
142 mov r3, lr
158 bx r3
/arm-trusted-firmware-2.8.0/include/arch/aarch32/
A Dsmccc_helpers.h42 u_register_t r3; member
99 CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
130 ((smc_ctx_t *)(_h))->r3 = (_r3); \
156 _r3 = ((smc_ctx_t *)_hdl)->r3; \
/arm-trusted-firmware-2.8.0/plat/allwinner/common/
A Darisc_off.S20 # r3, so to be patched in the lower 16 bits of the first instruction,
69 l.ff1 r6, r3 # get core number from high mask
83 l.movhi r3, 0 # FIXUP! with core mask
88 l.and r5, r5, r3 # mask requested core
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
/arm-trusted-firmware-2.8.0/lib/cpus/aarch32/
A Dcpu_helpers.S134 ldr r3, =CPU_IMPL_PN_MASK
137 and r2, r2, r3
145 and r1, r1, r3
/arm-trusted-firmware-2.8.0/include/arch/aarch64/
A Dsmccc_helpers.h119 register uint64_t r3 __asm__("x3") = arg2; in smc_helper()
127 : "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), "+r"(r4), in smc_helper()
133 ret_args._regs[3] = r3; in smc_helper()

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