Searched refs:sr (Results 1 – 9 of 9) sorted by relevance
36 unsigned sr; in __udivmoddi4() local97 ++sr; in __udivmoddi4()103 r.s.high = n.s.high >> sr; in __udivmoddi4()104 r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()115 sr = ctzsi(d.s.low); in __udivmoddi4()117 q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()127 if (sr == n_uword_bits) { in __udivmoddi4()136 r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()155 ++sr; in __udivmoddi4()166 r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); in __udivmoddi4()[all …]
20 // 0 <= sr <= N - 1 or sr is very large.21 if (sr > N - 1) // n < d25 ++sr;27 fixuint_t r = n >> sr;28 n <<= N - sr;30 for (; sr > 0; --sr) {49 // 0 <= sr <= N - 1 or sr is very large.54 ++sr;56 fixuint_t r = n >> sr;57 n <<= N - sr;[all …]
28 i2c_out(&ccsr_i2c->sr, I2C_SR_RST); in i2c_init()35 unsigned char sr; in wait_for_state() local40 sr = i2c_in(&ccsr_i2c->sr); in wait_for_state()41 if (sr & I2C_SR_AL) { in wait_for_state()42 i2c_out(&ccsr_i2c->sr, sr); in wait_for_state()46 if ((sr & mask) == state) { in wait_for_state()47 return (int)sr; in wait_for_state()64 i2c_out(&ccsr_i2c->sr, I2C_SR_IF); in tx_byte()109 i2c_out(&ccsr_i2c->sr, I2C_SR_IF); in i2c_write_addr()157 i2c_out(&ccsr_i2c->sr, I2C_SR_IF); in read_data()[all …]
64 static inline int spi_nor_read_sr(uint8_t *sr) in spi_nor_read_sr() argument86 uint8_t sr; in spi_nor_ready() local89 ret = spi_nor_read_sr(&sr); in spi_nor_ready()102 return (((fsr & FSR_READY) != 0U) && ((sr & SR_WIP) == 0U)) ? in spi_nor_ready()106 return (((sr & SR_WIP) == 0U) ? 0 : 1); in spi_nor_ready()126 uint8_t sr; in spi_nor_macronix_quad_enable() local129 ret = spi_nor_read_sr(&sr); in spi_nor_macronix_quad_enable()134 if ((sr & SR_QUAD_EN_MX) != 0U) { in spi_nor_macronix_quad_enable()143 sr |= SR_QUAD_EN_MX; in spi_nor_macronix_quad_enable()154 ret = spi_nor_read_sr(&sr); in spi_nor_macronix_quad_enable()[all …]
109 uint32_t sr; in stm32_rng_enable() local130 sr = mmio_read_32(stm32_rng.base + RNG_SR); in stm32_rng_enable()131 while ((sr & RNG_SR_DRDY) == 0U) { in stm32_rng_enable()137 if ((sr & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) { in stm32_rng_enable()143 sr = mmio_read_32(stm32_rng.base + RNG_SR); in stm32_rng_enable()
441 uint32_t sr; in stm32_pka_ecdsa_verif_check_return() local443 sr = mmio_read_32(base + _PKA_SR); in stm32_pka_ecdsa_verif_check_return()444 if ((sr & (_PKA_IT_OPERR | _PKA_IT_ADDRERR | _PKA_IT_RAMERR)) != 0) { in stm32_pka_ecdsa_verif_check_return()446 (sr & _PKA_IT_OPERR) ? "Operation " : "", in stm32_pka_ecdsa_verif_check_return()447 (sr & _PKA_IT_ADDRERR) ? "Address " : "", in stm32_pka_ecdsa_verif_check_return()448 (sr & _PKA_IT_RAMERR) ? "RAM" : ""); in stm32_pka_ecdsa_verif_check_return()
80 uint32_t rmsk, sr; in rcar_swdt_init() local132 sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; in rcar_swdt_init()133 mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE)); in rcar_swdt_init()
39 unsigned char sr; /* I2c Bus Status Register */ member
860 paxb = paxb_get_config(sr); in paxb_set_config()
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