Searched refs:tw_rin_clk_cycles (Results 1 – 2 of 2) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/soc/ |
| A D | agilex_memory_controller.c | 178 t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, in configure_ddr_sched_ctrl_regs() local
244 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
252 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
259 wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles) in configure_ddr_sched_ctrl_regs()
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/soc/ |
| A D | s10_memory_controller.c | 207 t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, in configure_ddr_sched_ctrl_regs() local
273 tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
281 tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? in configure_ddr_sched_ctrl_regs()
288 wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles) in configure_ddr_sched_ctrl_regs()
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