Searched refs:AMDGPU_IRQ_STATE_DISABLE (Results 1 – 25 of 27) sorted by relevance
12
42 AMDGPU_IRQ_STATE_DISABLE, enumerator
129 AMDGPU_IRQ_STATE_DISABLE); in amdgpu_irq_disable_all()508 state = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_irq_update()
597 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()613 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()
1007 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()1023 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()
190 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_vkms_crtc_init()
1114 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()1130 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()
1341 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()1357 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()
429 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_ecc_interrupt_state()481 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_vm_fault_interrupt_state()
2922 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()2973 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vline_interrupt_state()3001 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_hpd_interrupt_state()3116 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v8_0_set_pageflip_interrupt_state()
1038 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v6_0_vm_fault_interrupt_state()
3005 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()3034 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vline_interrupt_state()3064 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_hpd_irq_state()3142 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v10_0_set_pageflip_irq_state()
3204 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3225 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3267 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_reg_fault_state()3292 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_inst_fault_state()
63 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v11_0_vm_fault_interrupt_state()
3128 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()3157 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vline_interrupt_state()3187 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_hpd_irq_state()3265 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v11_0_set_pageflip_irq_state()
4666 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()4717 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_compute_eop_interrupt_state()4740 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_reg_fault_state()4765 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_inst_fault_state()
77 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v10_0_vm_fault_interrupt_state()
2874 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_crtc_vblank_interrupt_state()2909 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_hpd_interrupt_state()3024 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v6_0_set_pageflip_interrupt_state()
6414 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()6453 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_compute_eop_interrupt_state()6474 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()6485 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()6537 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_cp_ecc_int_state()6582 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_sq_int_state()
1233 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v7_0_vm_fault_interrupt_state()
5596 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5643 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_compute_eop_interrupt_state()5666 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_reg_fault_state()5685 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_inst_fault_state()5712 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_cp_ecc_error_state()
5794 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()5851 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_compute_eop_interrupt_state()5993 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_priv_reg_fault_state()6012 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v11_0_set_priv_inst_fault_state()6102 if (state == AMDGPU_IRQ_STATE_DISABLE) {
1401 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v8_0_vm_fault_interrupt_state()
3137 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()3154 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()
1338 case AMDGPU_IRQ_STATE_DISABLE: in smu_v11_0_set_irq_state()
1289 case AMDGPU_IRQ_STATE_DISABLE: in smu_v13_0_set_irq_state()
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