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Searched refs:CLK_SCLK_SPI0 (Results 1 – 19 of 19) sorted by relevance

/linux-6.3-rc2/arch/arm/boot/dts/
A Dexynos3250-artik5-eval.dts46 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
50 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
A Dexynos3250.dtsi828 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
A Dexynos4.dtsi621 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
A Dexynos5250.dtsi504 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
A Dexynos5420.dtsi662 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Dexynos5250.h51 #define CLK_SCLK_SPI0 154 macro
A Dexynos7-clk.h41 #define CLK_SCLK_SPI0 7 macro
A Dexynos4.h72 #define CLK_SCLK_SPI0 159 macro
A Dexynos5420.h36 #define CLK_SCLK_SPI0 135 macro
A Dexynos3250.h253 #define CLK_SCLK_SPI0 245 macro
A Dexynos5433.h434 #define CLK_SCLK_SPI0 33 macro
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos5250.c508 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
A Dclk-exynos3250.c560 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
A Dclk-exynos7.c352 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
A Dclk-exynos4.c789 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
A Dclk-exynos5420.c987 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
A Dclk-exynos5433.c1715 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
/linux-6.3-rc2/arch/arm64/boot/dts/exynos/
A Dexynos7.dtsi225 <&clock_top0 CLK_SCLK_SPI0>,
A Dexynos5433.dtsi1463 <&cmu_peric CLK_SCLK_SPI0>,

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