Searched refs:CLK_TOP_APLL1 (Results 1 – 20 of 20) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | mt8516-clk.h | 65 #define CLK_TOP_APLL1 33 macro
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| A D | mediatek,mt6795-clk.h | 36 #define CLK_TOP_APLL1 25 macro
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| A D | mt6765-clk.h | 76 #define CLK_TOP_APLL1 41 macro
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| A D | mt8173-clk.h | 35 #define CLK_TOP_APLL1 25 macro
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| A D | mediatek,mt8365-clk.h | 54 #define CLK_TOP_APLL1 44 macro
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| A D | mt2712-clk.h | 74 #define CLK_TOP_APLL1 43 macro
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| A D | mt8192-clk.h | 113 #define CLK_TOP_APLL1 101 macro
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| A D | mt8195-clk.h | 104 #define CLK_TOP_APLL1 92 macro
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| /linux-6.3-rc2/drivers/clk/mediatek/ |
| A D | clk-mt6795-topckgen.c | 386 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt8173-topckgen.c | 461 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt8516.c | 59 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt8195-topckgen.c | 1082 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
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| A D | clk-mt8167.c | 67 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt2712.c | 133 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
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| A D | clk-mt6765.c | 126 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt8192.c | 62 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| A D | clk-mt8365.c | 76 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
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| /linux-6.3-rc2/Documentation/devicetree/bindings/sound/ |
| A D | mt8195-afe-pcm.yaml | 161 <&topckgen 163>, //CLK_TOP_APLL1
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| /linux-6.3-rc2/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 879 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
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| A D | mt8192.dtsi | 875 <&topckgen CLK_TOP_APLL1>,
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