| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_afmt.c | 51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
82 *CTS = cts; in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
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| /linux-6.3-rc2/arch/arm64/boot/dts/freescale/ |
| A D | imx8mm-venice-gw72xx-0x-rs232-rts.dtso | 5 * GW72xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
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| A D | imx8mm-venice-gw73xx-0x-rs232-rts.dtso | 5 * GW73xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
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| A D | imx8mq-hummingboard-pulse.dts | 166 * reconfigured to enable RTS/CTS on UART3
209 * Header. To use RTS/CTS on UART3 comment them out
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| /linux-6.3-rc2/drivers/crypto/keembay/ |
| A D | Kconfig | 31 bool "Support for Intel Keem Bay OCS AES/SM4 CTS HW acceleration"
35 AES/SM4 CBC with CTS mode hardware acceleration for use with
40 Intel does not recommend use of CTS mode with AES/SM4.
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | imx6ull-dhcom-drc02.dts | 23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
24 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
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| A D | am335x-netcom-plus-2xx.dts | 25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
38 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
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| A D | imx6ul-ccimx6ulsbcpro.dts | 62 /* CAN2 is multiplexed with UART2 RTS/CTS */
201 /* UART2 RTS/CTS muxed with CAN2 */
209 /* UART3 RTS/CTS muxed with CAN 1 */
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| A D | ste-dbx5x0-pinctrl.dtsi | 17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
75 pins = "GPIO6_AF6"; /* CTS */
86 pins = "GPIO6_AF6"; /* CTS */
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| A D | stm32mp157a-iot-box.dts | 57 /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
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| /linux-6.3-rc2/Documentation/devicetree/bindings/serial/ |
| A D | serial.yaml | 32 the UART's CTS line.
68 for RTS/CTS hardware flow control, and that they are available for use
78 description: CTS and RTS pins are swapped.
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| A D | microchip,pic32-uart.txt | 14 - cts-gpios: CTS pin for UART
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| A D | cirrus,clps711x-uart.txt | 11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
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| A D | cdns,uart.yaml | 40 Override the CTS modem status signal. This signal will
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| /linux-6.3-rc2/Documentation/usb/ |
| A D | iuu_phoenix.rst | 44 0=none, 1=CD, 2=!CD, 3=DSR, 4=!DSR, 5=CTS, 6=!CTS, 7=RING, 8=!RING (int)
|
| /linux-6.3-rc2/arch/arm64/boot/dts/allwinner/ |
| A D | sun50i-a64-orangepi-win.dts | 382 /* On Pi-2 connector, RTS/CTS optional */
389 /* On Pi-2 connector, RTS/CTS optional */
396 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
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| A D | sun50i-a64-pine64.dts | 285 /* On Wifi/BT connector, with RTS/CTS */
306 /* On Euler connector, RTS/CTS optional */
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| /linux-6.3-rc2/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| A D | serial.txt | 14 CTS, RTS, DCD, DSR, DTR, and RI.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/crypto/ |
| A D | samsung-slimsss.yaml | 15 -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
| /linux-6.3-rc2/drivers/tty/ |
| A D | nozomi.c | 238 unsigned int CTS:1; member
299 unsigned int CTS:1; member
921 if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) { in receive_flow_control()
926 } else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) { in receive_flow_control()
944 if (old_ctrl.CTS != ctrl_dl.CTS) in receive_flow_control()
1618 if (port->ctrl_dl.CTS) { in ntty_write()
1668 | (ctrl_dl->CTS ? TIOCM_CTS : 0); in ntty_tiocmget()
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| /linux-6.3-rc2/drivers/net/hamradio/ |
| A D | z8530.h | 178 #define CTS 0x20 /* CTS */ macro
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| /linux-6.3-rc2/drivers/tty/serial/ |
| A D | zs.h | 234 #define CTS 0x20 /* CTS */ macro
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| A D | ip22zilog.h | 214 #define CTS 0x20 /* CTS */ macro
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| A D | sunzilog.h | 218 #define CTS 0x20 /* CTS */ macro
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| /linux-6.3-rc2/arch/arm64/boot/dts/renesas/ |
| A D | rzg2lc-smarc-pinfunction.dtsi | 61 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
|