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Searched refs:DPLL_CTL (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/arch/arm/mach-omap1/
A Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
A Dreset.c33 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_restart()
A Dclock_data.c732 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
/linux-6.3-rc2/include/linux/soc/ti/
A Domap1-io.h87 #define DPLL_CTL (0xfffecf00) macro

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