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Searched refs:IS_DG2 (Results 1 – 25 of 31) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_workarounds.c927 else if (IS_DG2(i915)) in __intel_engine_init_ctx_wa()
1355 if (IS_DG2(gt->i915)) in xehp_init_mcr()
1776 else if (IS_DG2(i915)) in gt_init_workarounds()
2285 else if (IS_DG2(i915)) in intel_engine_init_whitelist()
2521 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || in rcs_engine_wa_init()
2984 if (IS_DG2(i915)) { in add_render_compute_tuning_settings()
3030 IS_DG2(i915)) { in general_render_compute_wa_init()
3037 IS_DG2(i915)) { in general_render_compute_wa_init()
3099 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { in general_render_compute_wa_init()
3107 if (IS_DG2(i915)) { in general_render_compute_wa_init()
A Dintel_gt_mcr.c190 } else if (IS_DG2(i915)) { in intel_gt_mcr_init()
615 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
A Dintel_gsc.c192 } else if (IS_DG2(i915)) { in gsc_init_one()
A Dintel_mocs.c455 } else if (IS_DG2(i915)) { in get_mocs_settings()
A Dintel_reset.c643 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
A Dintel_lrc.c1373 if (IS_DG2(ce->engine->i915)) in gen12_emit_indirect_ctx_rcs()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_hwmon.c297 if (IS_DG1(i915) || IS_DG2(i915)) in hwm_pcode_read_i1()
317 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; in hwm_in_is_visible()
646 if (IS_DG1(i915) || IS_DG2(i915)) { in hwm_get_preregistration_info()
A Di915_drv.h563 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) macro
723 (IS_DG2(__i915) && \
830 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
A Di915_perf.c2808 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_enable_metric_set()
2897 if (IS_XEHPSDV(i915) || IS_DG2(i915)) { in gen12_disable_metric_set()
3147 if (IS_DG2(i915) || IS_METEORLAKE(i915)) { in i915_perf_oa_timestamp_frequency()
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_dmc.c331 if (IS_DG2(i915)) { in get_flip_queue_event_regs()
349 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) in disable_all_flip_queue_events()
940 if (IS_DG2(dev_priv)) { in intel_dmc_ucode_init()
A Dintel_cdclk.c1458 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
2456 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { in intel_crtc_compute_min_cdclk()
3348 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
A Dintel_display_power.c921 if (IS_DG2(dev_priv)) in get_allowed_dc_mask()
1666 if (IS_DG2(dev_priv)) in icl_display_core_init()
A Dintel_bw.c632 else if (IS_DG2(dev_priv)) in intel_bw_init_hw()
A Dintel_ddi_buf_trans.c1614 if (IS_DG2(i915)) { in intel_ddi_buf_trans_init()
A Dintel_ddi.c198 if (IS_DG2(dev_priv)) { in intel_wait_ddi_buf_active()
4399 if (IS_DG2(dev_priv)) { in intel_ddi_init()
4457 if (IS_DG2(dev_priv)) { in intel_ddi_init()
A Dintel_fbc.c815 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915)) in intel_fbc_program_workarounds()
A Dintel_display_power_well.c261 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { in hsw_wait_for_power_well_enable()
A Dintel_snps_phy.c1942 if (!IS_DG2(i915)) in intel_mpllb_state_verify()
A Dskl_watermark.c1308 if (IS_DG2(i915)) in skl_compute_dbuf_slices()
3222 int mult = IS_DG2(i915) ? 2 : 1; in skl_read_wm_latency()
A Dintel_display.c994 if (IS_DG2(dev_priv)) in icl_set_pipe_chicken()
2069 if (IS_DG2(dev_priv)) in intel_phy_is_tc()
2086 else if (IS_DG2(dev_priv)) in intel_phy_is_snps()
7878 if (IS_DG2(dev_priv)) { in intel_setup_outputs()
A Dintel_dpll.c1520 if (IS_DG2(dev_priv)) in intel_dpll_init_clock_hook()
/linux-6.3-rc2/drivers/gpu/drm/i915/soc/
A Dintel_pch.c223 } else if (IS_DG2(dev_priv)) { in intel_detect_pch()
A Dintel_dram.c510 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc.c280 IS_DG2(gt->i915)) in guc_ctl_wa_flags()
290 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
A Dintel_guc_capture.c421 if (IS_DG2(i915)) in guc_capture_get_device_reglist()

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