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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 82) sorted by relevance

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/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/
A Dport.c161 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon()
172 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_ib_port_oper()
203 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_set_port_admin_status()
217 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_query_port_admin_status()
234 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; in mlx5_query_port_mtu()
251 u32 out[MLX5_ST_SZ_DW(pmtu_reg)]; in mlx5_set_port_mtu()
277 u32 out[MLX5_ST_SZ_DW(pmlp_reg)]; in mlx5_query_module_num()
297 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; in mlx5_query_module_id()
378 u32 out[MLX5_ST_SZ_DW(mcia_reg)]; in mlx5_query_mcia()
673 u32 in[MLX5_ST_SZ_DW(qtct_reg)]; in mlx5_query_port_prio_tc()
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A Dtransobj.c68 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {}; in mlx5_core_create_rq()
91 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; in mlx5_core_destroy_rq()
101 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {}; in mlx5_core_query_rq()
112 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {}; in mlx5_core_create_sq()
133 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; in mlx5_core_destroy_sq()
142 u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {}; in mlx5_core_query_sq()
198 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {}; in mlx5_core_destroy_tir()
277 u32 in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; in mlx5_hairpin_create_rq()
296 u32 in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; in mlx5_hairpin_create_sq()
355 u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {}; in mlx5_hairpin_modify_rq()
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A Dmr.c40 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {}; in mlx5_core_create_mkey()
61 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {}; in mlx5_core_destroy_mkey()
72 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {}; in mlx5_core_query_mkey()
94 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {}; in mlx5_core_create_psv()
95 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {}; in mlx5_core_create_psv()
118 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {}; in mlx5_core_destroy_psv()
A Dfw.c415 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
416 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
433 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_query()
434 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_query()
460 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; in mlx5_reg_mcda_set()
490 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {}; in mlx5_reg_mcqi_query()
659 u32 out[MLX5_ST_SZ_DW(mirc_reg)]; in mlx5_fsm_reactivate()
660 u32 in[MLX5_ST_SZ_DW(mirc_reg)]; in mlx5_fsm_reactivate()
746 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {}; in mlx5_reg_mcqs_query()
761 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {}; in mlx5_get_boot_img_component_index()
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A Decpf.c22 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_host_pf_enable_hca()
23 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_host_pf_enable_hca()
33 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_host_pf_disable_hca()
34 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_host_pf_disable_hca()
A Dpd.c39 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in mlx5_core_alloc_pd()
40 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in mlx5_core_alloc_pd()
53 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_core_dealloc_pd()
A Dfs_cmd.c169 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; in mlx5_cmd_set_slave_root_fdb()
214 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {}; in mlx5_cmd_update_root_ft()
269 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {}; in mlx5_cmd_create_flow_table()
270 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {}; in mlx5_cmd_create_flow_table()
336 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {}; in mlx5_cmd_destroy_flow_table()
359 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {}; in mlx5_cmd_modify_flow_table()
405 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {}; in mlx5_cmd_create_flow_group()
427 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {}; in mlx5_cmd_destroy_flow_group()
509 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0}; in mlx5_cmd_set_fte()
744 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {}; in mlx5_cmd_delete_fte()
[all …]
A Dqos.c29 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_leaf_node()
44 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_inner_node()
68 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_update_node()
A Dcq.c94 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_create_cq()
165 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_core_destroy_cq()
191 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {}; in mlx5_core_query_cq()
202 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {}; in mlx5_core_modify_cq()
215 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {}; in mlx5_core_modify_cq_moderation()
A Dmcg.c40 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {}; in mlx5_core_attach_mcg()
53 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {}; in mlx5_core_detach_mcg()
A Dvport.c46 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {}; in mlx5_query_vport_state()
47 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {}; in mlx5_query_vport_state()
67 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {}; in mlx5_modify_vport_admin_state()
82 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in mlx5_query_nic_vport_context()
96 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {}; in mlx5_query_nic_vport_min_inline()
128 u32 in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {}; in mlx5_modify_nic_vport_min_inline()
150 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in mlx5_query_nic_vport_mac_address()
259 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; in mlx5_query_nic_vport_mac_list()
372 u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)]; in mlx5_modify_nic_vport_vlans()
1002 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; in mlx5_query_vport_down_stats()
[all …]
/linux-6.3-rc2/drivers/infiniband/hw/mlx5/
A Dcmd.c59 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {}; in mlx5_cmd_destroy_tir()
69 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_cmd_destroy_tis()
79 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {}; in mlx5_cmd_destroy_rqt()
120 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_cmd_dealloc_pd()
131 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {}; in mlx5_cmd_attach_mcg()
158 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {}; in mlx5_cmd_xrcd_alloc()
159 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {}; in mlx5_cmd_xrcd_alloc()
172 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {}; in mlx5_cmd_xrcd_dealloc()
219 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {}; in mlx5_cmd_uar_alloc()
220 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {}; in mlx5_cmd_uar_alloc()
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A Dqpc.c193 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {}; in _mlx5_core_destroy_dct()
243 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_qpc_create_qp()
275 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {}; in mlx5_core_drain_dct()
292 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_core_destroy_qp()
510 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {}; in mlx5_core_qp_query()
522 u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {}; in mlx5_core_dct_query()
534 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {}; in mlx5_core_xrcd_alloc()
535 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {}; in mlx5_core_xrcd_alloc()
556 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; in destroy_rq_tracked()
598 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; in destroy_sq_tracked()
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A Dsrq_cmd.c166 u32 in[MLX5_ST_SZ_DW(destroy_srq_in)] = {}; in destroy_srq_cmd()
178 u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {}; in arm_srq_cmd()
192 u32 in[MLX5_ST_SZ_DW(query_srq_in)] = {}; in query_srq_cmd()
220 u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)]; in create_xrc_srq_cmd()
273 u32 in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {}; in destroy_xrc_srq_cmd()
285 u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {}; in arm_xrc_srq_cmd()
301 u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {}; in query_xrc_srq_cmd()
388 u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {}; in destroy_rmp_cmd()
537 u32 in[MLX5_ST_SZ_DW(destroy_xrq_in)] = {}; in destroy_xrq_cmd()
550 u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {}; in arm_xrq_cmd()
[all …]
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/sf/
A Dcmd.c9 u32 out[MLX5_ST_SZ_DW(alloc_sf_out)] = {}; in mlx5_cmd_alloc_sf()
10 u32 in[MLX5_ST_SZ_DW(alloc_sf_in)] = {}; in mlx5_cmd_alloc_sf()
20 u32 out[MLX5_ST_SZ_DW(dealloc_sf_out)] = {}; in mlx5_cmd_dealloc_sf()
21 u32 in[MLX5_ST_SZ_DW(dealloc_sf_in)] = {}; in mlx5_cmd_dealloc_sf()
31 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_sf_enable_hca()
32 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_sf_enable_hca()
42 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_sf_disable_hca()
43 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_sf_disable_hca()
A Dvhca_event.c26 u32 in[MLX5_ST_SZ_DW(query_vhca_state_in)] = {}; in mlx5_cmd_query_vhca_state()
38 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_cmd_modify_vhca_state()
49 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_modify_vhca_sw_id()
50 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_modify_vhca_sw_id()
63 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_vhca_event_arm()
74 u32 out[MLX5_ST_SZ_DW(query_vhca_state_out)] = {}; in mlx5_vhca_event_notify()
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/fpga/
A Dcmd.c75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
127 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
128 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
145 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)] = {}; in mlx5_fpga_create_qp()
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {}; in mlx5_fpga_create_qp()
167 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {}; in mlx5_fpga_modify_qp()
181 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)] = {}; in mlx5_fpga_query_qp()
182 u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {}; in mlx5_fpga_query_qp()
[all …]
/linux-6.3-rc2/drivers/vdpa/mlx5/core/
A Dresources.c12 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in alloc_pd()
13 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in alloc_pd()
28 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in dealloc_pd()
53 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; in create_uctx()
84 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; in destroy_uctx()
97 u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {}; in mlx5_vdpa_create_tis()
111 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_vdpa_destroy_tis()
121 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {}; in mlx5_vdpa_create_rqt()
134 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {}; in mlx5_vdpa_modify_rqt()
144 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {}; in mlx5_vdpa_destroy_rqt()
[all …]
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/steering/
A Ddr_cmd.c12 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {}; in mlx5dr_cmd_query_esw_vport_context()
13 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {}; in mlx5dr_cmd_query_esw_vport_context()
37 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {}; in mlx5dr_cmd_query_gvmi()
215 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {}; in mlx5dr_cmd_query_flow_table()
216 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {}; in mlx5dr_cmd_query_flow_table()
272 u32 in[MLX5_ST_SZ_DW(sync_steering_in)] = {}; in mlx5dr_cmd_sync_steering()
293 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {}; in mlx5dr_cmd_set_fte_modify_and_vport()
334 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {}; in mlx5dr_cmd_del_flow_table_entry()
443 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {}; in mlx5dr_cmd_create_flow_table()
635 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5dr_cmd_destroy_definer()
[all …]
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/en/
A Dport.c113 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_proto()
133 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_autoneg()
150 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
151 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
293 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_query_sbpr()
305 u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
306 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
322 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_query_sbcm()
336 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm()
545 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_in_caps()
[all …]
A Dtir.c12 MLX5_ST_SZ_DW(create_tir_in) > MLX5_ST_SZ_DW(modify_tir_in) ? \
13 MLX5_ST_SZ_DW(create_tir_in) : MLX5_ST_SZ_DW(modify_tir_in) \
A Dmonitor_stats.c41 u32 in[MLX5_ST_SZ_DW(arm_monitor_counter_in)] = {}; in mlx5e_monitor_counter_arm()
107 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_set_monitor_counter()
143 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_monitor_counter_cleanup()
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/diag/
A Dfs_tracepoint.h109 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
110 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
111 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
193 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
194 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
195 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
196 __array(u32, value_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
197 __array(u32, value_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
198 __array(u32, value_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
A Dfw_tracer.c42 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
43 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
86 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_set_mtrc_caps_trace_owner()
97 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_acquire()
118 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_release()
270 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_tracer_read_strings_db()
345 u32 out[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
346 u32 in[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
773 u32 out[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
774 u32 in[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
[all …]
/linux-6.3-rc2/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dgeneve.c22 u32 in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {}; in mlx5_geneve_tlv_option_create()
23 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_create()
53 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
54 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()

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