/linux-6.3-rc2/arch/sh/kernel/cpu/sh4a/ |
A D | clock-sh7724.c | 28 #define MSTPCR2 0xa4150038 macro 234 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), 235 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), 249 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), 250 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), 251 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 252 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 253 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 254 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), 255 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), [all …]
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A D | clock-sh7723.c | 27 #define MSTPCR2 0xa4150038 macro 173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0), 181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 184 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 185 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), 186 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 187 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 188 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 189 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), 190 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), [all …]
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A D | clock-sh7343.c | 23 #define MSTPCR2 0xa4150038 macro 166 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), 167 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), 168 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), 169 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), 171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), 175 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 177 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 178 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 179 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), [all …]
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A D | clock-sh7366.c | 23 #define MSTPCR2 0xa4150038 macro 166 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), 167 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), 168 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), 169 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), 170 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), 171 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), 175 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 176 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 177 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), [all …]
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A D | clock-sh7722.c | 26 #define MSTPCR2 0xa4150038 macro 156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 158 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), 159 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 160 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), 161 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 162 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 163 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 164 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), 165 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), [all …]
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A D | clock-sh7757.c | 77 #define MSTPCR2 0xffc10028 macro 99 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
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/linux-6.3-rc2/arch/sh/boot/romimage/ |
A D | mmcif-sh7724.c | 16 #define MSTPCR2 0xa4150038 macro 42 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader() 75 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
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/linux-6.3-rc2/arch/sh/include/cpu-sh4/cpu/ |
A D | freq.h | 21 #define MSTPCR2 0xa4150038 macro 45 #define MSTPCR2 0xa4150038 macro
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