Home
last modified time | relevance | path

Searched refs:PACKET3_SET_SH_REG (Results 1 – 12 of 12) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h267 #define PACKET3_SET_SH_REG 0x76 macro
A Dsoc15d.h294 #define PACKET3_SET_SH_REG 0x76 macro
A Dnvd.h330 #define PACKET3_SET_SH_REG 0x76 macro
A Dvid.h346 #define PACKET3_SET_SH_REG 0x76 macro
A Dcikd.h464 #define PACKET3_SET_SH_REG 0x76 macro
A Dgfx_v9_4_2.c381 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_4_2_run_shader()
389 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_4_2_run_shader()
396 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3); in gfx_v9_4_2_run_shader()
A Dgfx_v8_0.c1543 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1569 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1595 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1601 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
A Dgfx_v9_0.c4390 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4397 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4418 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4425 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
4446 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_0_do_edc_gpr_workarounds()
4453 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_0_do_edc_gpr_workarounds()
A Dsid.h1853 #define PACKET3_SET_SH_REG 0x76 macro
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dsid.h1790 #define PACKET3_SET_SH_REG 0x76 macro
A Dcikd.h1932 #define PACKET3_SET_SH_REG 0x76 macro
A Dsi.c4573 case PACKET3_SET_SH_REG: in si_vm_packet3_gfx_check()
4676 case PACKET3_SET_SH_REG: in si_vm_packet3_compute_check()

Completed in 78 milliseconds