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Searched refs:PLL15 (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/Documentation/devicetree/bindings/sound/
A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
38 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
A Dti,j721e-cpb-audio.yaml20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
29 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/linux-6.3-rc2/include/dt-bindings/clock/
A Dqcom,mmcc-msm8960.h135 #define PLL15 126 macro
/linux-6.3-rc2/drivers/clk/qcom/
A Dmmcc-msm8960.c2985 [PLL15] = &pll15.clkr,

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