Searched refs:PLL_VPLL (Results 1 – 20 of 20) sorted by relevance
| /linux-6.3-rc2/arch/arm64/boot/dts/rockchip/ |
| A D | rk3566-anbernic-rg353x.dtsi | 19 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-anbernic-rg503.dts | 108 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-radxa-cm3-io.dts | 259 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-box-demo.dts | 469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-lubancat-1.dts | 582 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-roc-pc.dts | 688 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-soquartz.dtsi | 678 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3568-evb1-v10.dts | 679 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3568-lubancat-2.dts | 682 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-quartz64-b.dts | 726 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3568-odroid-m1.dts | 731 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3568-bpi-r2-pro.dts | 842 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-anbernic-rgxx3.dtsi | 773 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3568-rock-3a.dts | 845 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3566-quartz64-a.dts | 826 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
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| A D | rk3399.dtsi | 1932 <&cru PLL_VPLL>;
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| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | rk3399-cru.h | 17 #define PLL_VPLL 7 macro
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| A D | rk3568-cru.h | 74 #define PLL_VPLL 5 macro
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| /linux-6.3-rc2/drivers/clk/rockchip/ |
| A D | clk-rk3399.c | 231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
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| A D | clk-rk3568.c | 336 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
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