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Searched refs:SCLK_NANDC (Results 1 – 18 of 18) sorted by relevance

/linux-6.3-rc2/Documentation/devicetree/bindings/mtd/
A Drockchip,nand-controller.yaml137 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
139 assigned-clocks = <&clks SCLK_NANDC>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Drk3036-cru.h22 #define SCLK_NANDC 76 macro
A Drk3128-cru.h21 #define SCLK_NANDC 67 macro
A Drk3228-cru.h19 #define SCLK_NANDC 67 macro
A Drv1108-cru.h18 #define SCLK_NANDC 67 macro
A Dpx30-cru.h57 #define SCLK_NANDC 55 macro
A Drk3308-cru.h49 #define SCLK_NANDC 45 macro
/linux-6.3-rc2/drivers/clk/rockchip/
A Dclk-rk3036.c340 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
A Dclk-rk3128.c451 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
A Dclk-rk3228.c501 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
A Dclk-rv1108.c734 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
A Dclk-px30.c474 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
A Dclk-rk3308.c483 …COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARE…
/linux-6.3-rc2/arch/arm/boot/dts/
A Drk3036.dtsi318 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
320 assigned-clocks = <&cru SCLK_NANDC>;
A Drv1108.dtsi463 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
465 assigned-clocks = <&cru SCLK_NANDC>;
A Drk3128.dtsi178 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
/linux-6.3-rc2/arch/arm64/boot/dts/rockchip/
A Dpx30.dtsi299 <&cru SCLK_NANDC>,
1049 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1051 assigned-clocks = <&cru SCLK_NANDC>;
A Drk3308.dtsi703 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
705 assigned-clocks = <&cru SCLK_NANDC>;

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