Home
last modified time | relevance | path

Searched refs:SDMA0_PHASE0_QUANTUM__VALUE__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dcik_sdma.c351 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in cik_ctx_switch_enable()
358 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in cik_ctx_switch_enable()
366 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in cik_ctx_switch_enable()
A Dsdma_v3_0.c558 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v3_0_ctx_switch_enable()
565 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v3_0_ctx_switch_enable()
573 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v3_0_ctx_switch_enable()
A Dsdma_v5_2.c409 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v5_2_ctx_switch_enable()
416 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v5_2_ctx_switch_enable()
424 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v5_2_ctx_switch_enable()
A Dsdma_v5_0.c606 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v5_0_ctx_switch_enable()
613 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v5_0_ctx_switch_enable()
621 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v5_0_ctx_switch_enable()
A Dsdma_v4_0.c946 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v4_0_ctx_switch_enable()
953 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v4_0_ctx_switch_enable()
961 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v4_0_ctx_switch_enable()
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma0/
A Dsdma0_4_1_sh_mask.h596 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
A Dsdma0_4_0_sh_mask.h597 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
A Dsdma0_4_2_sh_mask.h599 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
A Dsdma0_4_2_2_sh_mask.h605 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/oss/
A Doss_2_0_sh_mask.h1014 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
A Doss_2_4_sh_mask.h1104 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
A Doss_3_0_1_sh_mask.h1124 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
A Doss_3_0_sh_mask.h1630 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma/
A Dsdma_4_4_0_sh_mask.h292 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
A Dgc_10_1_0_sh_mask.h311 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
A Dgc_10_3_0_sh_mask.h312 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro

Completed in 899 milliseconds