Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 12 of 12) sorted by relevance
/linux-6.3-rc2/drivers/gpu/drm/radeon/ |
A D | cik_sdma.c | 73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr() 97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr() 118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr() 262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop() 312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable() 344 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable() 379 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume() 492 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() 495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode() 508 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() [all …]
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A D | cik.c | 166 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register() 4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs() 4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset() 4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset() 4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset() 5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset() 5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset() 5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable() 6170 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg() 6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state() [all …]
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A D | cikd.h | 1953 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
A D | cik_sdma.c | 50 SDMA1_REGISTER_OFFSET 885 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg() 895 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg() 913 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls() 923 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls() 1079 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset() 1081 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset() 1131 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state() 1133 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state() 1136 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state() [all …]
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A D | sdma_v2_4.c | 63 SDMA1_REGISTER_OFFSET 971 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset() 973 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset() 1024 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1026 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state() 1029 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1031 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
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A D | amdgpu_amdkfd_gfx_v7.c | 139 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset() 297 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
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A D | sdma_v3_0.c | 77 SDMA1_REGISTER_OFFSET 1358 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1360 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state() 1363 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1365 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
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A D | amdgpu_amdkfd_gfx_v8.c | 134 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset() 320 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
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A D | vid.h | 27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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A D | cikd.h | 485 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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A D | cik.c | 1053 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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A D | vi.c | 679 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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