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Searched refs:SR (Results 1 – 25 of 157) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_hwseq.h116 SR(BLNDV_CONTROL),\
158 SR(DCHUB_AGP_BASE),\
159 SR(DCHUB_AGP_BOT),\
160 SR(DCHUB_AGP_TOP)
172 SR(REFCLK_CNTL), \
177 SR(DCFCLK_CNTL),\
178 SR(DCFCLK_CNTL), \
250 SR(MPC_CRC_CTRL), \
393 SR(REFCLK_CNTL), \
398 SR(DCFCLK_CNTL),\
[all …]
A Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
51 SR(DC_DMCU_SCRATCH)
55 SR(DMCU_CTRL), \
56 SR(DMCU_STATUS), \
68 SR(DC_DMCU_SCRATCH)
72 SR(DMCU_CTRL), \
73 SR(DMCU_STATUS), \
86 SR(DC_DMCU_SCRATCH)
94 SR(DMU_MEM_PWR_CNTL)
[all …]
A Ddce_abm.h33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
46 SR(BL1_PWM_USER_LEVEL), \
50 SR(DC_ABM1_ACE_THRES_12), \
51 SR(BIOS_SCRATCH_2)
74 SR(DC_ABM1_HG_MISC_CTRL), \
78 SR(BL1_PWM_USER_LEVEL), \
[all …]
A Ddce_panel_cntl.h39 SR(BL_PWM_CNTL), \
40 SR(BL_PWM_CNTL2), \
41 SR(BL_PWM_PERIOD_CNTL), \
42 SR(BL_PWM_GRP1_REG_LOCK), \
43 SR(BIOS_SCRATCH_2)
53 SR(BL_PWM_CNTL), \
54 SR(BL_PWM_CNTL2), \
55 SR(BL_PWM_PERIOD_CNTL), \
56 SR(BL_PWM_GRP1_REG_LOCK), \
A Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
A Ddce_link_encoder.h48 SR(DMCU_RAM_ACCESS_CTRL), \
49 SR(DMCU_IRAM_RD_CTRL), \
50 SR(DMCU_IRAM_RD_DATA), \
51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
77 SR(DCI_MEM_PWR_STATUS)
82 SR(DMCU_RAM_ACCESS_CTRL), \
83 SR(DMCU_IRAM_RD_CTRL), \
84 SR(DMCU_IRAM_RD_DATA), \
115 SR(DCI_MEM_PWR_STATUS)
122 SR(DCI_MEM_PWR_STATUS)
[all …]
A Ddce_i2c_hw.h88 SR(DC_I2C_ARBITRATION),\
89 SR(DC_I2C_CONTROL),\
90 SR(DC_I2C_SW_STATUS),\
91 SR(DC_I2C_TRANSACTION0),\
92 SR(DC_I2C_TRANSACTION1),\
93 SR(DC_I2C_TRANSACTION2),\
94 SR(DC_I2C_TRANSACTION3),\
95 SR(DC_I2C_DATA),\
96 SR(MICROSECOND_TIME_BASE_DIV)
100 SR(DIO_MEM_PWR_CTRL),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/
A Ddcn32_hubbub.h41 SR(DCHUBBUB_SOFT_RESET),\
42 SR(DCHUBBUB_CRC_CTRL), \
45 SR(DCN_VM_FB_OFFSET),\
46 SR(DCN_VM_AGP_BOT),\
47 SR(DCN_VM_AGP_TOP),\
48 SR(DCN_VM_AGP_BASE),\
62 SR(DCHUBBUB_DET0_CTRL),\
63 SR(DCHUBBUB_DET1_CTRL),\
64 SR(DCHUBBUB_DET2_CTRL),\
65 SR(DCHUBBUB_DET3_CTRL),\
[all …]
A Ddcn32_dccg.h36 SR(DPPCLK_DTO_CTRL),\
42 SR(PHYASYMCLK_CLOCK_CNTL),\
43 SR(PHYBSYMCLK_CLOCK_CNTL),\
44 SR(PHYCSYMCLK_CLOCK_CNTL),\
47 SR(DPSTREAMCLK_CNTL),\
48 SR(HDMISTREAMCLK_CNTL),\
49 SR(SYMCLK32_SE_CNTL),\
50 SR(SYMCLK32_LE_CNTL),\
65 SR(OTG_PIXEL_RATE_DIV),\
66 SR(DTBCLK_P_CNTL),\
[all …]
A Ddcn32_resource.h1224 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL), \
1225 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
1226 SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL), \
1227 SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP), \
1228 SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP), \
1230 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B), \
1231 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C), SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D), \
1239 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D), SR(DCHUBBUB_DET0_CTRL), \
1240 SR(DCHUBBUB_DET1_CTRL), SR(DCHUBBUB_DET2_CTRL), SR(DCHUBBUB_DET3_CTRL), \
1270 SR(PHYESYMCLK_CLOCK_CNTL), SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL), \
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_hubbub.h33 SR(DCHVM_CTRL0),\
34 SR(DCHVM_MEM_CTRL),\
35 SR(DCHVM_CLK_CTRL),\
36 SR(DCHVM_RIOMMU_CTRL0),\
37 SR(DCHVM_RIOMMU_STAT0),\
38 SR(DCHUBBUB_DET0_CTRL),\
39 SR(DCHUBBUB_DET1_CTRL),\
40 SR(DCHUBBUB_DET2_CTRL),\
41 SR(DCHUBBUB_DET3_CTRL),\
45 SR(DCHUBBUB_CLOCK_CNTL),\
[all …]
A Ddcn31_dccg.h32 SR(DPPCLK_DTO_CTRL),\
37 SR(PHYASYMCLK_CLOCK_CNTL),\
38 SR(PHYBSYMCLK_CLOCK_CNTL),\
42 SR(DPSTREAMCLK_CNTL),\
43 SR(SYMCLK32_SE_CNTL),\
44 SR(SYMCLK32_LE_CNTL),\
60 SR(DENTIST_DISPCLK_CNTL),\
61 SR(DSCCLK0_DTO_PARAM),\
62 SR(DSCCLK1_DTO_PARAM),\
63 SR(DSCCLK2_DTO_PARAM),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dwb.h33 SR(FC_MODE_CTRL),\
34 SR(FC_FLOW_CTRL),\
35 SR(FC_WINDOW_START),\
36 SR(FC_WINDOW_SIZE),\
37 SR(FC_SOURCE_SIZE),\
38 SR(DWB_UPDATE_CTRL),\
39 SR(DWB_CRC_CTRL),\
42 SR(DWB_CRC_VAL_R_G),\
43 SR(DWB_CRC_VAL_B_A),\
44 SR(DWB_OUT_CTRL),\
[all …]
A Ddcn30_hubbub.h40 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
41 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
42 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
43 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
44 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
45 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
46 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
47 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
48 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
49 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
[all …]
A Ddcn30_dccg.h34 SR(PHYASYMCLK_CLOCK_CNTL),\
35 SR(PHYBSYMCLK_CLOCK_CNTL),\
36 SR(PHYCSYMCLK_CLOCK_CNTL)
45 SR(PHYASYMCLK_CLOCK_CNTL),\
46 SR(PHYBSYMCLK_CLOCK_CNTL),\
47 SR(PHYCSYMCLK_CLOCK_CNTL)
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hubbub.h46 SR(DCHUBBUB_ARB_SAT_LEVEL),\
48 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
49 SR(DCHUBBUB_TEST_DEBUG_INDEX), \
50 SR(DCHUBBUB_TEST_DEBUG_DATA),\
51 SR(DCHUBBUB_SOFT_RESET)
73 SR(DCHUBBUB_SDPIF_FB_TOP),\
74 SR(DCHUBBUB_SDPIF_FB_BASE),\
75 SR(DCHUBBUB_SDPIF_FB_OFFSET),\
76 SR(DCHUBBUB_SDPIF_AGP_BASE),\
77 SR(DCHUBBUB_SDPIF_AGP_BOT),\
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_hubbub.h31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
43 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
44 SR(DCHVM_CTRL0), \
45 SR(DCHVM_MEM_CTRL), \
46 SR(DCHVM_CLK_CTRL), \
47 SR(DCHVM_RIOMMU_CTRL0), \
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/
A Ddcn314_dccg.h37 SR(DPPCLK_DTO_CTRL),\
48 SR(DPSTREAMCLK_CNTL),\
49 SR(HDMISTREAMCLK_CNTL),\
50 SR(SYMCLK32_SE_CNTL),\
51 SR(SYMCLK32_LE_CNTL),\
68 SR(DSCCLK0_DTO_PARAM),\
69 SR(DSCCLK1_DTO_PARAM),\
70 SR(DSCCLK2_DTO_PARAM),\
71 SR(DSCCLK_DTO_CTRL),\
75 SR(OTG_PIXEL_RATE_DIV),\
[all …]
A Ddcn314_resource.c159 #define SR(reg_name)\ macro
702 SR(DIO_MEM_PWR_CTRL), \
708 SR(DCFCLK_CNTL),\
727 SR(MPC_CRC_CTRL), \
747 SR(D1VGA_CONTROL), \
748 SR(D2VGA_CONTROL), \
749 SR(D3VGA_CONTROL), \
750 SR(D4VGA_CONTROL), \
751 SR(D5VGA_CONTROL), \
752 SR(D6VGA_CONTROL), \
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hubbub.h37 SR(DCHUBBUB_CRC_CTRL), \
38 SR(DCN_VM_FB_LOCATION_BASE),\
39 SR(DCN_VM_FB_LOCATION_TOP),\
40 SR(DCN_VM_FB_OFFSET),\
41 SR(DCN_VM_AGP_BOT),\
42 SR(DCN_VM_AGP_TOP),\
43 SR(DCN_VM_AGP_BASE),\
44 SR(DCN_VM_FAULT_ADDR_MSB), \
45 SR(DCN_VM_FAULT_ADDR_LSB), \
46 SR(DCN_VM_FAULT_CNTL), \
[all …]
/linux-6.3-rc2/Documentation/translations/zh_CN/PCI/
A Dpci-iov-howto.rst28 什么是SR-IOV
31 单根I/O虚拟化（SR-IOV）是一种PCI Express扩展功能，它使一个物理设备显示为多个
42 我怎样才能启用SR-IOV功能
45 有多种方法可用于SR-IOV的启用。在第一种方法中，设备驱动（PF驱动）将通过SR-IOV
46 核心提供的API控制功能的启用和禁用。如果硬件具有SR-IOV能力，加载其PF驱动器将启
63 SR-IOV API
66 用来开启SR-IOV功能:
79 用来关闭SR-IOV功能:
90 要想通过主机上的兼容驱动启用自动探测VF，在启用SR-IOV功能之前运行下面的命令。这
97 要禁止主机上的兼容驱动自动探测VF，请在启用SR-IOV功能之前运行以下命令。更新这个
[all …]
/linux-6.3-rc2/Documentation/networking/
A Dseg6-sysctl.rst12 Accept or drop SR-enabled IPv6 packets on this interface.
20 Define HMAC policy for ingress SR-enabled packets on this interface.
23 * 0 - Accept SR packets without HMAC, validate SR packets with HMAC
24 * 1 - Drop SR packets without HMAC, validate SR packets with HMAC
30 IPv6 header in case of SR T.encaps
/linux-6.3-rc2/Documentation/PCI/
A Dpci-iov-howto.rst15 What is SR-IOV
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
37 Multiple methods are available for SR-IOV enablement.
40 If the hardware has SR-IOV capability, loading its PF driver would
63 SR-IOV API
66 To enable SR-IOV capability:
79 To disable SR-IOV capability:
91 command below before enabling SR-IOV capabilities. This is the
99 command below before enabling SR-IOV capabilities. Updating this
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/
A Ddcn316_resource.c149 #define SR(reg_name)\ macro
676 SR(DIO_MEM_PWR_CTRL), \
682 SR(DCFCLK_CNTL),\
701 SR(MPC_CRC_CTRL), \
719 SR(D1VGA_CONTROL), \
720 SR(D2VGA_CONTROL), \
721 SR(D3VGA_CONTROL), \
722 SR(D4VGA_CONTROL), \
723 SR(D5VGA_CONTROL), \
724 SR(D6VGA_CONTROL), \
[all …]
/linux-6.3-rc2/drivers/macintosh/
A Dvia-cuda.c349 (void)in_8(&via[SR]); in sync_egret()
364 (void)in_8(&via[SR]); in sync_egret()
401 (void)in_8(&via[SR]); in cuda_init_via()
412 (void)in_8(&via[SR]); in cuda_init_via()
421 (void)in_8(&via[SR]); in cuda_init_via()
602 (void)in_8(&via[SR]); in cuda_interrupt()
612 (void)in_8(&via[SR]); in cuda_interrupt()
623 (void)in_8(&via[SR]); in cuda_interrupt()
642 (void)in_8(&via[SR]); in cuda_interrupt()
666 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]

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