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/linux-6.3-rc2/Documentation/devicetree/bindings/serial/
A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
24 respectively the UART sum interrupt, the UART TX interrupt and
25 UART RX interrupt. A corresponding interrupt-names property must
29 respectively the UART TX interrupt and the UART RX interrupt. A
33 containing only the UART sum interrupt. This form is deprecated
A Dcirrus,clps711x-uart.txt1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
14 Note: Each UART port should have an alias correctly numbered
A Dnvidia,tegra194-tcu.yaml7 title: NVIDIA Tegra Combined UART (TCU)
14 The TCU is a system for sharing a hardware UART instance among multiple
16 based protocol where each "virtual UART" has a pair of mailboxes, one
40 transmitting data from and to the hardware UART.
42 - description: mailbox for receiving data from hardware UART
43 - description: mailbox for transmitting data to hardware UART
A Dserial.yaml18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
32 the UART's CTS line.
38 the UART's DCD line.
44 the UART's DSR line.
50 the UART's DTR line.
56 the UART's RNG line.
62 the UART's RTS line.
67 The presence of this property indicates that the UART has dedicated lines
70 UART hardware and the board wiring.
104 Serial attached devices shall be a child node of the host UART device
[all …]
A Darc-uart.txt1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
A Dnvidia,tegra20-hsuart.txt1 NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
10 - reg: Should contain UART controller registers location and length.
11 - interrupts: Should contain UART controller interrupts.
26 only if all 8 lines of UART controller are pinmuxed.
37 Standard UART devices are expected to have tolerance for baud rate error by
39 Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
52 This slight deviation is expcted and Tegra UART is expected to handle it. Due
53 to the issue stated above, baud rate on Tegra UART should be set equal to or
A Drenesas,em-uart.yaml7 title: Renesas EMMA Mobile UART Interface
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
A Darm,mps2-uart.txt1 ARM MPS2 UART
6 - interrupts : Reference to the UART RX, TX and overrun interrupts
9 - clocks : The input clock of the UART
A Dsifive-serial.yaml7 title: SiFive asynchronous serial interface (UART)
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
A Dsprd-uart.yaml8 title: Spreadtrum serial UART
38 "enable" for UART module enable clock, "uart" for UART clock, "source"
39 for UART source (parent) clock.
A Damlogic,meson-uart.yaml8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
37 - description: Everything-Else power domain UART controller
64 description: The fifo size supported by the UART channel.
A Dmediatek,uart.yaml7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
52 description: The base address of the UART register bank
83 The UART interrupt and optionally the RX in-band wakeup interrupt.
/linux-6.3-rc2/arch/arm/mach-sa1100/include/mach/
A Duncompress.h21 #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) macro
29 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
31 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
33 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
38 while (!(UART(UTSR1) & UTSR1_TNF)) in putc()
42 UART(UTDR) = c; in putc()
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dmarvell,armada-3700-uart-clock.yaml6 title: Marvell Armada 3720 UART clocks
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
22 List of parent clocks suitable for UART from following set:
24 UART clock can use one from this set and when more are provided
28 used for UART (most probably xtal) for smooth boot log on UART.
/linux-6.3-rc2/Documentation/devicetree/bindings/dma/
A Dmediatek,uart-dma.yaml7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
38 TX, RX interrupt lines for each UART APDMA channel
52 The first cell specifies the UART APDMA channel number
56 Number of virtual channels of the UART APDMA controller
61 description: Enable 33-bits UART APDMA support
/linux-6.3-rc2/arch/arm/
A DKconfig.debug370 on HI3620 UART.
386 on HIP01 UART.
394 on HIP04 UART.
402 on Hix5hd2 UART.
405 bool "i.MX1 Debug UART"
412 bool "i.MX23 Debug UART"
420 bool "i.MX25 Debug UART"
427 bool "i.MX27 Debug UART"
1064 on SD5203 UART.
1226 are UART A/B/C/D/E.
[all …]
/linux-6.3-rc2/arch/arm/include/debug/
A Dtegra.S85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
91 cmp \rv, #0 @ UART 0?
93 cmp \rv, #1 @ UART 1?
95 cmp \rv, #2 @ UART 2?
97 cmp \rv, #3 @ UART 3?
99 cmp \rv, #4 @ UART 4?
141 cmp \rp, #0 @ Valid UART address?
/linux-6.3-rc2/Documentation/ABI/testing/
A Dsysfs-platform-kim6 Name of the UART device at which the WL128x chip
21 UART configurations, so the baud-rate needs to be set
32 entry most often should be 1, the host's UART is required
42 use of the shared UART transport, it registers to the shared
46 daemon managing the UART, and is notified about the change
47 by the sysfs_notify. The value would be '1' when UART needs
48 to be opened/ldisc installed, and would be '0' when UART
A Dsysfs-bus-i2c-devices-fsa948010 UART UART is attached
23 UART switch to UART path
/linux-6.3-rc2/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
A Ducc.txt15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
21 broken UART hardware. Soft-UART is provided via a microcode upload.
/linux-6.3-rc2/Documentation/devicetree/bindings/net/
A Dqca,qca7000.txt4 be configured either as SPI or UART slave. This configuration is done by
58 (b) Ethernet over UART
60 In order to use the QCA7000 as UART slave it must be defined as a child of a
61 UART master in the device tree. It is possible to preconfigure the UART
73 UART Example:
75 /* Freescale i.MX28 UART */
A Dmediatek-bluetooth.txt37 MediaTek UART based Bluetooth Devices
40 This device is a serial attached device to UART device and thus it must be a
41 child node of the serial node with UART.
58 - pinctrl-0: Should contain UART RXD low when the device is powered up to
60 - pinctrl-1: Should contain UART mode pin ctrl
66 - boot-gpios: GPIO same to the pin as UART RXD and used to keep LOW when
69 - pinctrl-0: Should contain UART mode pin ctrl
/linux-6.3-rc2/drivers/tty/serial/
A DKconfig959 tristate "SiFive UART support"
965 contains a SiFive UART IP block. This type of UART is present on
969 bool "Console on SiFive UART"
995 bool "Console on Lantiq UART"
1131 tristate "Altera UART support"
1194 UART (AUART) port.
1253 bool "MPS2 UART port"
1267 bool "Console on ARC UART"
1275 int "Number of ARC UART ports"
1541 tristate "Sunplus UART support"
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/linux-6.3-rc2/arch/mips/
A DKconfig.debug102 int "UART to use for compressed kernel debugging"
107 Specify the UART that should be used for compressed kernel debugging.
127 bool "CPS SMP NS16550 UART output"
130 Output debug information via an ns16550 compatible UART if exceptions
139 hex "UART Base Address"
143 The base address of the ns16550 compatible UART on which to output
149 int "UART Register Shift"
157 int "UART Register Width"
160 ns16550 registers width. UART registers IO access methods will be
162 4 UART registers will be accessed by means of lb/sb, lh/sh or lw/sw
/linux-6.3-rc2/Documentation/devicetree/bindings/soc/aspeed/
A Duart-routing.yaml9 title: Aspeed UART Routing Controller
16 The Aspeed UART routing control allow to dynamically route the inputs for
19 This allows, for example, to connect the output of UART to another UART.

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