Home
last modified time | relevance | path

Searched refs:VC4_MASK (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/vc4/
A Dvc4_regs.h12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) macro
170 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
172 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
176 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
178 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
182 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
184 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
188 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
800 VC4_MASK(5, 4)
808 VC4_MASK(7, 6)
[all …]
A Dvc4_packet.h183 #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)
195 #define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)
202 #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)
205 #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)
258 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5)
265 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3)
285 #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)
292 #define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)
333 #define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9)
335 #define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8)
[all …]
A Dvc4_hdmi_phy.c46 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)
60 #define VC4_HDMI_TX_PHY_CTL_3_RP_MASK VC4_MASK(19, 17)
62 #define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK VC4_MASK(16, 12)
64 #define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK VC4_MASK(11, 10)
66 #define VC4_HDMI_TX_PHY_CTL_3_CP_MASK VC4_MASK(9, 8)
68 #define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK VC4_MASK(7, 6)
70 #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)
92 #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK VC4_MASK(15, 8)
95 #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)
123 #define VC4_HDMI_RM_OFFSET_OFFSET_MASK VC4_MASK(30, 0)
[all …]
A Dvc4_dsi.c53 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
58 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
74 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
99 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
129 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
154 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
158 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
171 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
476 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
484 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
[all …]
A Dvc4_dpi.c36 # define DPI_ORDER_MASK VC4_MASK(15, 14)
46 # define DPI_FORMAT_MASK VC4_MASK(13, 11)
A Dvc4_hdmi.c61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
[all …]

Completed in 24 milliseconds