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Searched refs:X86_CONFIG (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/arch/x86/kernel/cpu/resctrl/
A Dpseudo_lock.c1073 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1075 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1112 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
1114 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
/linux-6.3-rc2/arch/x86/events/zhaoxin/
A Dcore.c570 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
573 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
/linux-6.3-rc2/arch/x86/events/intel/
A Dcore.c3703 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
4453 X86_CONFIG(.event=0xc0, .umask=0x01)) { in bdw_limit_period()
6013 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6016 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6201 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6204 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6241 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6244 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6282 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6475 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init()
[all …]
/linux-6.3-rc2/arch/x86/events/
A Dperf_event.h643 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro

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