| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_cdclk.c | 584 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
673 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
792 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
1074 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1385 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1689 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1808 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
1960 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2127 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2146 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
[all …]
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| A D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
80 …k_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
82 …k_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
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| A D | intel_audio.c | 524 unsigned int fec_coeff, cdclk, vdsc_bpp; in calc_hblank_early_prog() local
532 cdclk = i915->display.cdclk.hw.cdclk; in calc_hblank_early_prog()
540 h_active, link_clk, lanes, vdsc_bpp, cdclk); in calc_hblank_early_prog()
542 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
551 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
552 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
986 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
993 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
1001 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
1146 return i915->display.cdclk.hw.cdclk; in i915_audio_component_get_cdclk_freq()
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| A D | hsw_ips.c | 203 crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
242 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
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| A D | intel_display_core.h | 265 const struct intel_cdclk_funcs *cdclk; member
321 } cdclk; member
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| A D | intel_dp_aux.c | 87 freq = dev_priv->display.cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
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| A D | intel_modeset_setup.c | 37 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_crtc_disable_noatomic()
434 to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_readout_hw_state()
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| A D | intel_backlight.c | 1105 clock = KHz(i915->display.cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1123 clock = KHz(i915->display.cdclk.hw.cdclk); in i965_hz_to_pwm()
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| A D | intel_display.c | 2628 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
4731 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
8352 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_modeset_init_hw()
8355 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_modeset_init_hw()
8356 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_modeset_init_hw()
8727 if (i915->display.cdclk.max_cdclk_freq == 0) in intel_modeset_init_nogem()
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| A D | intel_fbc.c | 1159 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
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| A D | intel_display_power_well.c | 975 intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw, in gen9_disable_dc_states()
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| A D | intel_display_power.c | 1322 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
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| A D | intel_dpll_mgr.c | 1850 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
3966 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
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| A D | intel_dp.c | 744 i915->display.cdclk.max_cdclk_freq * 48 / in intel_dp_dsc_get_output_bpp()
1588 if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq || in intel_dp_dsc_compute_config()
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| /linux-6.3-rc2/drivers/clk/samsung/ |
| A D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
105 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
119 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
120 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| A D | clk-exynos-audss.c | 129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
189 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
191 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
192 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| /linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
| A D | samsung,exynos-audss-clock.yaml | 52 - const: cdclk
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /linux-6.3-rc2/drivers/gpu/drm/i915/gt/ |
| A D | intel_gt_pm_debugfs.c | 396 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in intel_gt_pm_frequency_dump()
397 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in intel_gt_pm_frequency_dump()
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | s3c64xx-pinctrl.dtsi | 334 i2s0_cdclk: i2s0-cdclk-pins {
346 i2s1_cdclk: i2s1-cdclk-pins {
360 i2s2_cdclk: i2s2-cdclk-pins {
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