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Searched refs:clk_set_parent (Results 1 – 25 of 100) sorted by relevance

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/linux-6.3-rc2/drivers/clk/imx/
A Dclk-imx6sx.c177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
542 clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk); in imx6sx_clocks_init()
548 clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); in imx6sx_clocks_init()
[all …]
A Dclk-imx6q.c275 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
499 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
501 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
502 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
503 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
975 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
977 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init()
980 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
982 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, in imx6q_clocks_init()
[all …]
A Dclk-imx6ul.c178 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
179 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
180 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
182 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
183 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
184 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
513 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk); in imx6ul_clocks_init()
515 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk); in imx6ul_clocks_init()
521 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
[all …]
A Dclk-vf610.c236 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init()
237 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init()
238 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init()
239 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init()
240 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init()
241 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init()
242 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init()
457 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
458 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
459 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
[all …]
A Dclk-cpu.c48 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate()
55 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
59 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
A Dclk-imx6sl.c234 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
235 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
236 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
237 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
238 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
239 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
240 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
434 clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); in imx6sl_clocks_init()
437 clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, in imx6sl_clocks_init()
440 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, in imx6sl_clocks_init()
A Dclk-imx5.c277 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init()
347 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
348 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
438 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
441 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
442 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
592 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
593 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
600 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
603 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
/linux-6.3-rc2/sound/soc/mediatek/mt8183/
A Dmt8183-afe-clk.c134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
[all …]
/linux-6.3-rc2/drivers/cpufreq/
A Dtegra124-cpufreq.c38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
44 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
49 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
142 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpufreq_suspend()
168 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpufreq_resume()
A Dimx6q-cpufreq.c128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
130 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
133 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
136 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
139 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
142 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
143 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
146 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
A Dimx-cpufreq-dt.c66 clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
67 clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
70 clk_set_parent(imx7ulp_clks[ARM].clk, in imx7ulp_target_intermediate()
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
A Dkirkwood-cpufreq.c65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
68 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
A Dmediatek-cpufreq.c265 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
278 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
284 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
301 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
303 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
/linux-6.3-rc2/sound/soc/mediatek/mt8186/
A Dmt8186-afe-clk.c81 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8186_set_audio_int_bus_parent()
105 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
121 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
130 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
140 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
166 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
182 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
201 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
267 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8186_afe_enable_clock()
287 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], in mt8186_afe_enable_clock()
[all …]
/linux-6.3-rc2/sound/soc/mediatek/mt8192/
A Dmt8192-afe-clk.c69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
231 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8192_afe_enable_clock()
255 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], in mt8192_afe_enable_clock()
[all …]
/linux-6.3-rc2/sound/soc/samsung/
A Dsmdk_spdif.c55 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy()
56 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy()
57 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
/linux-6.3-rc2/sound/soc/sof/mediatek/mt8195/
A Dmt8195-clk.c121 ret = clk_set_parent(priv->clk[CLK_TOP_ADSP], in adsp_default_clk_init()
128 ret = clk_set_parent(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS], in adsp_default_clk_init()
135 ret = clk_set_parent(priv->clk[CLK_TOP_AUDIO_H], in adsp_default_clk_init()
/linux-6.3-rc2/arch/m68k/coldfire/
A Dclk.c130 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
135 EXPORT_SYMBOL(clk_set_parent);
/linux-6.3-rc2/drivers/clk/ti/
A Dclk-33xx.c294 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
297 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
307 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
/linux-6.3-rc2/arch/mips/lantiq/
A Dclk.c168 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
172 EXPORT_SYMBOL(clk_set_parent);
/linux-6.3-rc2/drivers/clk/mmp/
A Dclk-pxa910.c206 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
217 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
228 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
A Dclk-mmp2.c246 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
257 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
268 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
279 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
A Dclk-pxa168.c201 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
212 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
223 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
/linux-6.3-rc2/drivers/devfreq/
A Dimx8m-ddrc.c193 ret = clk_set_parent(priv->dram_core, new_dram_core_parent); in imx8m_ddrc_set_freq()
197 ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent); in imx8m_ddrc_set_freq()
203 ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent); in imx8m_ddrc_set_freq()
/linux-6.3-rc2/drivers/gpu/drm/imx/ipuv3/
A Dimx-ldb.c187 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
209 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
210 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
215 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
354 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()

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