cntval_mask (reference) in projects: linux-6.3-rc2

Searched refs:cntval_mask (Results 1 – 9 of 9) sorted by relevance

/linux-6.3-rc2/arch/x86/events/intel/
A D	p6.c	`226 .cntval_mask = (1ULL << 32) - 1,`
A D	knc.c	`308 .cntval_mask = (1ULL << 40) - 1,`
A D	p4.c	`1026 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in p4_pmu_set_period() 1359 .cntval_mask = ARCH_P4_CNTRVAL_MASK,`
A D	ds.c	`1366 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()`
A D	core.c	`5919 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init() 6759 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()`
/linux-6.3-rc2/arch/x86/events/zhaoxin/
A D	core.c	`535 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in zhaoxin_pmu_init() 552 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in zhaoxin_pmu_init()`
/linux-6.3-rc2/arch/x86/events/amd/
A D	core.c	`1252 .cntval_mask = (1ULL << 48) - 1,`
/linux-6.3-rc2/arch/x86/events/
A D	perf_event.h	`767 u64 cntval_mask; member`
A D	core.c	`1412 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period() 2050 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in x86_pmu_show_pmu_cap()`

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