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Searched refs:cpt_write_csr64 (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/drivers/crypto/cavium/cpt/
A Dcptpf_mbox.c12 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), in cpt_send_msg_to_vf()
14 cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); in cpt_send_msg_to_vf()
31 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); in cpt_clear_mbox_intr()
44 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); in cpt_cfg_qlen_for_vf()
56 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); in cpt_cfg_vq_priority()
79 cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u); in cpt_bind_vq_to_grp()
A Dcptpf_main.c39 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_disable_cores()
55 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), in cpt_disable_cores()
72 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), in cpt_enable_cores()
86 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), in cpt_configure_group()
100 cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); in cpt_disable_ecc_interrupts()
106 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); in cpt_disable_exec_interrupts()
152 cpt_write_csr64(cpt->reg_base, in cpt_load_microcode()
349 cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1); in cpt_reset()
388 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0); in cpt_disable_all_cores()
403 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0); in cpt_disable_all_cores()
[all …]
A Dcptvf_main.c378 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0), in cptvf_write_vq_doorbell()
398 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), in cptvf_write_vq_done_numwait()
409 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), in cptvf_write_vq_done_timewait()
421 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), in cptvf_enable_swerr_interrupts()
433 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), in cptvf_enable_mbox_interrupts()
457 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), in cptvf_clear_dovf_intr()
469 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), in cptvf_clear_irde_intr()
481 cpt_write_csr64(cptvf->reg_base, in cptvf_clear_nwrp_intr()
493 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), in cptvf_clear_mbox_intr()
505 cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), in cptvf_clear_swerr_intr()
[all …]
A Dcptvf_mbox.c11 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0), in cptvf_send_msg_to_pf()
13 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1), in cptvf_send_msg_to_pf()
A Dcpt_common.h143 static inline void cpt_write_csr64(u8 __iomem *hw_addr, u64 offset, in cpt_write_csr64() function

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