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Searched refs:crtc_state (Results 1 – 25 of 303) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_color.c281 (crtc_state->hw.degamma_lut || crtc_state->hw.ctm); in ilk_lut_limited_range()
1746 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
1862 crtc_state->csc_enable = ilk_csc_enable(crtc_state); in ilk_color_check()
1864 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
1866 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
1968 crtc_state->csc_enable = ilk_csc_enable(crtc_state); in ivb_color_check()
1970 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
1972 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
2101 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); in glk_color_check()
2169 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); in icl_color_check()
[all …]
A Dintel_vrr.c85 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; in intel_vrr_vblank_exit_length()
91 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
96 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
137 crtc_state->vrr.vmax = vmax; in intel_vrr_compute_config()
140 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; in intel_vrr_compute_config()
153 crtc_state->vrr.guardband = in intel_vrr_compute_config()
183 if (!crtc_state->vrr.enable) in intel_vrr_enable()
202 if (!crtc_state->vrr.enable) in intel_vrr_send_push()
215 if (!crtc_state->vrr.enable) in intel_vrr_is_push_sent()
248 if (!crtc_state->vrr.enable) in intel_vrr_get_config()
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A Dintel_modeset_setup.c48 if (!crtc_state->hw.active) in intel_crtc_disable_noatomic()
92 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); in intel_crtc_disable_noatomic()
151 crtc_state->uapi.enable = crtc_state->hw.enable; in intel_crtc_copy_hw_to_uapi_state()
152 crtc_state->uapi.active = crtc_state->hw.active; in intel_crtc_copy_hw_to_uapi_state()
156 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; in intel_crtc_copy_hw_to_uapi_state()
157 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; in intel_crtc_copy_hw_to_uapi_state()
335 crtc_state->hw.active; in intel_sanitize_encoder()
337 if (crtc_state && has_bogus_dpll_config(crtc_state)) { in intel_sanitize_encoder()
356 if (crtc_state) { in intel_sanitize_encoder()
454 crtc_state->hw.enable = crtc_state->hw.active; in intel_modeset_readout_hw_state()
[all …]
A Dintel_dpll.c1155 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1162 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1235 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1261 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1303 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1306 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1341 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1344 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1377 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1380 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
[all …]
A Dintel_atomic.c242 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
243 if (!crtc_state) in intel_crtc_duplicate_state()
251 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
253 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
256 if (crtc_state->pre_csc_lut) in intel_crtc_duplicate_state()
271 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
273 crtc_state->dsb = NULL; in intel_crtc_duplicate_state()
275 return &crtc_state->uapi; in intel_crtc_duplicate_state()
311 kfree(crtc_state); in intel_crtc_destroy_state()
471 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
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A Dintel_ddi_buf_trans.c1226 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1255 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1280 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1305 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1383 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1396 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1427 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1470 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1481 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
1509 if (crtc_state->port_clock > 270000) in adlp_get_combo_buf_trans_dp()
[all …]
A Dintel_ddi.c577 crtc_state)); in intel_ddi_enable_transcoder_func()
2827 crtc_state); in trans_port_sync_stop_link_train()
2982 crtc_state, in intel_enable_ddi()
3074 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3080 if (crtc_state && crtc_state->hw.active) { in intel_ddi_update_prepare()
3521 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3590 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
3631 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) in intel_ddi_sync_state()
3779 crtc_state)) in intel_ddi_port_sync_transcoders()
3797 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
[all …]
A Dintel_dp_link_training.c375 if (intel_dp_is_uhbr(crtc_state)) in intel_dp_get_lane_adjust_train()
421 crtc_state->lane_count, in intel_dp_get_adjust_train()
429 crtc_state->lane_count, in intel_dp_get_adjust_train()
464 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
541 crtc_state->lane_count, in intel_dp_set_signal_levels()
549 crtc_state->lane_count, in intel_dp_set_signal_levels()
877 if (intel_dp_is_uhbr(crtc_state)) in intel_dp_training_pattern()
983 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
1102 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1120 crtc_state->port_clock, in intel_dp_schedule_fallback_link_training()
[all …]
A Dintel_pch_display.c348 ilk_fdi_pll_enable(crtc_state); in ilk_pch_pre_enable()
383 if (crtc_state->shared_dpll == in ilk_pch_enable()
416 &crtc_state->hw.adjusted_mode; in ilk_pch_enable()
494 &crtc_state->fdi_m_n); in ilk_pch_clock_get()
510 crtc_state->has_pch_encoder = true; in ilk_pch_get_config()
517 &crtc_state->fdi_m_n); in ilk_pch_get_config()
534 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
541 crtc_state->pixel_multiplier = in ilk_pch_get_config()
545 ilk_pch_clock_get(crtc_state); in ilk_pch_get_config()
608 lpt_program_iclkip(crtc_state); in lpt_pch_enable()
[all …]
A Dhsw_ips.c18 if (!crtc_state->ips_enabled) in hsw_ips_enable()
27 !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); in hsw_ips_enable()
60 if (!crtc_state->ips_enabled) in hsw_ips_disable()
192 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
213 struct intel_crtc_state *crtc_state = in hsw_ips_compute_config() local
216 crtc_state->ips_enabled = false; in hsw_ips_compute_config()
218 if (!hsw_crtc_state_ips_capable(crtc_state)) in hsw_ips_compute_config()
227 if (crtc_state->crc_enabled) in hsw_ips_compute_config()
231 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) in hsw_ips_compute_config()
246 crtc_state->ips_enabled = true; in hsw_ips_compute_config()
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A Dintel_ddi.h26 const struct intel_crtc_state *crtc_state);
28 const struct intel_crtc_state *crtc_state);
34 const struct intel_crtc_state *crtc_state);
37 struct intel_crtc_state *crtc_state,
40 const struct intel_crtc_state *crtc_state);
44 struct intel_crtc_state *crtc_state);
47 const struct intel_crtc_state *crtc_state);
53 const struct intel_crtc_state *crtc_state);
56 const struct intel_crtc_state *crtc_state);
64 struct intel_crtc_state *crtc_state);
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A Dintel_crtc.c153 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_state_alloc()
155 if (crtc_state) in intel_crtc_state_alloc()
158 return crtc_state; in intel_crtc_state_alloc()
164 memset(crtc_state, 0, sizeof(*crtc_state)); in intel_crtc_state_reset()
185 if (!crtc_state) { in intel_crtc_alloc()
191 crtc->config = crtc_state; in intel_crtc_alloc()
387 return crtc_state->hw.active && in intel_crtc_needs_vblank_work()
389 !crtc_state->preload_luts && in intel_crtc_needs_vblank_work()
402 intel_color_load_luts(crtc_state); in intel_crtc_vblank_work()
404 if (crtc_state->uapi.event) { in intel_crtc_vblank_work()
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A Dintel_vdsc.c615 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
622 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
639 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
646 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
664 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
671 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
689 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
696 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
714 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
721 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
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A Dintel_display.c3002 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
4767 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4769 crtc_state->linetime = hsw_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4778 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, in hsw_compute_linetime_wm()
5042 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state_modeset()
5043 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state_modeset()
5048 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; in intel_crtc_copy_uapi_to_hw_state_modeset()
5158 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); in intel_crtc_prepare_cleared_state()
5302 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
5307 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); in intel_modeset_pipe_config()
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A Dintel_hdmi.c715 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
719 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
722 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
774 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
839 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
1037 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
2070 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, in hdmi_bpc_possible()
2126 crtc_state->port_clock = in intel_hdmi_compute_clock()
2134 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2214 crtc_state->output_format = in intel_hdmi_compute_output_format()
[all …]
A Dintel_audio.c257 &crtc_state->hw.adjusted_mode; in audio_config_hdmi_pixel_clock()
289 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
323 u32 *eld = (u32 *)crtc_state->eld; in g4x_audio_codec_get_config()
536 lanes = crtc_state->lane_count; in calc_hblank_early_prog()
574 lanes = crtc_state->lane_count; in calc_samples_room()
781 &crtc_state->hw.adjusted_mode; in intel_audio_compute_config()
791 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); in intel_audio_compute_config()
819 if (!crtc_state->has_audio) in intel_audio_codec_enable()
830 crtc_state, in intel_audio_codec_enable()
853 crtc_state->port_clock, in intel_audio_codec_enable()
[all …]
A Dintel_color.h19 int intel_color_check(struct intel_crtc_state *crtc_state);
20 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state);
21 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
22 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
23 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
24 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
25 void intel_color_get_config(struct intel_crtc_state *crtc_state);
26 bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
30 void intel_color_assert_luts(const struct intel_crtc_state *crtc_state);
A Dskl_scaler.c109 &crtc_state->scaler_state; in skl_update_scaler()
113 &crtc_state->hw.adjusted_mode; in skl_update_scaler()
225 if (crtc_state->pch_pfit.enabled) { in skl_update_scaler_crtc()
232 return skl_update_scaler(crtc_state, !crtc_state->hw.active, in skl_update_scaler_crtc()
234 &crtc_state->scaler_state.scaler_id, in skl_update_scaler_crtc()
235 drm_rect_width(&crtc_state->pipe_src), in skl_update_scaler_crtc()
238 crtc_state->pch_pfit.enabled); in skl_update_scaler_crtc()
438 &crtc_state->scaler_state; in skl_pfit_enable()
451 if (!crtc_state->pch_pfit.enabled) in skl_pfit_enable()
474 crtc_state->hw.scaling_filter); in skl_pfit_enable()
[all …]
A Dintel_drrs.c132 crtc_state->bigjoiner_pipes) in intel_drrs_frontbuffer_bits()
148 if (!crtc_state->has_drrs) in intel_drrs_activate()
151 if (!crtc_state->hw.active) in intel_drrs_activate()
160 crtc->drrs.m_n = crtc_state->dp_m_n; in intel_drrs_activate()
317 str_yes_no(crtc_state->has_drrs)); in intel_drrs_debugfs_status_show()
342 struct intel_crtc_state *crtc_state; in intel_drrs_debugfs_ctl_set() local
352 if (!crtc_state->hw.active || in intel_drrs_debugfs_ctl_set()
353 !crtc_state->has_drrs) in intel_drrs_debugfs_ctl_set()
356 commit = crtc_state->uapi.commit; in intel_drrs_debugfs_ctl_set()
367 intel_drrs_activate(crtc_state); in intel_drrs_debugfs_ctl_set()
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A Dintel_psr.c832 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
990 if (crtc_state->vrr.enable) in intel_psr_compute_config()
1029 crtc_state->has_psr = true; in intel_psr_compute_config()
1030 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1278 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1810 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
1953 if (!crtc_state->has_psr) in _intel_psr_post_plane_update()
2124 if (IS_ERR(crtc_state)) { in intel_psr_fastset_force()
2125 err = PTR_ERR(crtc_state); in intel_psr_fastset_force()
2616 if (!crtc_state->has_psr) in intel_psr_lock()
[all …]
A Dintel_dp.h49 const struct intel_crtc_state *crtc_state);
51 const struct intel_crtc_state *crtc_state,
66 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
92 const struct intel_crtc_state *crtc_state,
96 const struct intel_crtc_state *crtc_state,
99 const struct intel_crtc_state *crtc_state,
102 struct intel_crtc_state *crtc_state,
128 const struct intel_crtc_state *crtc_state,
132 struct intel_crtc_state *crtc_state);
134 const struct intel_crtc_state *crtc_state);
[all …]
A Dintel_dp_mst.c65 &crtc_state->hw.adjusted_mode; in intel_dp_mst_find_vcpi_slots_for_bpp()
92 crtc_state->pbn); in intel_dp_mst_find_vcpi_slots_for_bpp()
116 crtc_state->pipe_bpp = bpp; in intel_dp_mst_find_vcpi_slots_for_bpp()
145 &crtc_state->dp_m_n, in intel_dp_mst_compute_link_config()
147 crtc_state->dp_m_n.tu = slots; in intel_dp_mst_compute_link_config()
239 &crtc_state->dp_m_n, in intel_dp_dsc_mst_compute_link_config()
390 if (!crtc_state->hw.active) in intel_dp_mst_transcoder_mask()
457 if (IS_ERR(crtc_state)) { in intel_dp_mst_atomic_master_trans_check()
458 ret = PTR_ERR(crtc_state); in intel_dp_mst_atomic_master_trans_check()
1224 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; in intel_dp_mst_is_master_trans()
[all …]
A Dintel_vdsc.h16 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
17 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
18 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
19 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
21 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
26 const struct intel_crtc_state *crtc_state);
28 const struct intel_crtc_state *crtc_state);
/linux-6.3-rc2/drivers/gpu/drm/vkms/
A Dvkms_composer.c83 struct vkms_crtc_state *crtc_state, in blend() argument
143 struct vkms_crtc_state *crtc_state, in compose_active_planes() argument
158 if (WARN_ON(check_iosys_map(crtc_state))) in compose_active_planes()
214 frame_start = crtc_state->frame_start; in vkms_composer_worker()
215 frame_end = crtc_state->frame_end; in vkms_composer_worker()
216 crc_pending = crtc_state->crc_pending; in vkms_composer_worker()
217 wb_pending = crtc_state->wb_pending; in vkms_composer_worker()
218 crtc_state->frame_start = 0; in vkms_composer_worker()
219 crtc_state->frame_end = 0; in vkms_composer_worker()
220 crtc_state->crc_pending = false; in vkms_composer_worker()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/gma500/
A Dgma_display.c506 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
580 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save() local
585 if (!crtc_state) { in gma_crtc_save()
593 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
594 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
623 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_restore() local
628 if (!crtc_state) { in gma_crtc_restore()
635 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
640 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore()
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