Searched refs:divn_shift (Results 1 – 6 of 6) sorted by relevance
| /linux-6.3-rc2/drivers/clk/tegra/ |
| A D | clk-tegra124.c | 146 .divn_shift = 8,
242 .divn_shift = 8,
316 .divn_shift = 8,
405 .divn_shift = 8,
464 .divn_shift = 8,
503 .divn_shift = 8,
531 .divn_shift = 8,
596 .divn_shift = 8,
713 .divn_shift = 8,
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| A D | clk-tegra114.c | 142 .divn_shift = 8,
204 .divn_shift = 8,
276 .divn_shift = 8,
324 .divn_shift = 8,
450 .divn_shift = 8,
548 .divn_shift = 8,
577 .divn_shift = 8,
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| A D | clk-tegra210.c | 1405 #define divn_shift(p) ((p)->params->div_nmp->divn_shift) macro
1569 .divn_shift = 8,
1691 .divn_shift = 10,
1737 .divn_shift = 10,
1806 .divn_shift = 8,
1884 .divn_shift = 8,
1958 .divn_shift = 8,
1995 .divn_shift = 8,
2028 .divn_shift = 10,
2094 .divn_shift = 8,
[all …]
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| A D | clk-pll.c | 253 #define divn_shift(p) (p)->params->div_nmp->divn_shift macro
257 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
268 .divn_shift = PLL_BASE_DIVN_SHIFT,
683 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
991 val |= sel.n << divn_shift(pll); in clk_plle_enable()
1025 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1654 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1943 .divn_shift = PLLE_BASE_DIVN_SHIFT,
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
[all …]
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| A D | clk.h | 199 u8 divn_shift; member
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| A D | clk-tegra30.c | 371 .divn_shift = 8,
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