/linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
A D | intel_dpll.c | 326 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m() 775 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument 777 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp() 782 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp() 875 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll() 932 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll() 1000 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune() 1110 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll() 1552 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local 1940 const struct dpll *dpll) in vlv_force_pll_on() argument [all …]
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A D | intel_dpll.h | 11 struct dpll; 23 int vlv_calc_dpll_params(int refclk, struct dpll *clock); 24 int pnv_calc_dpll_params(int refclk, struct dpll *clock); 25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock); 26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll); 31 const struct dpll *dpll); 41 struct dpll *best_clock); 42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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A D | intel_dpll_mgr.c | 453 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state() 563 hw_state->dpll, in ibx_dump_hw_state() 2132 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers() 2150 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers() 2170 const struct dpll *clk_div) in bxt_ddi_set_dpll_hw_state() 2241 struct dpll clock; in bxt_ddi_pll_get_freq() 2257 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state() 2268 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state() 4387 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks() 4436 if (dev_priv->display.dpll.mgr) { in intel_dpll_dump_hw_state() [all …]
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A D | intel_pch_refclk.c | 470 dev_priv->display.dpll.pch_ssc_use = 0; in lpt_init_pch_refclk() 474 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk() 479 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk() 484 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk() 487 if (dev_priv->display.dpll.pch_ssc_use) in lpt_init_pch_refclk() 536 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
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A D | intel_dvo.c | 409 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init_dev() local 448 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init_dev() 450 dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init_dev() 457 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init_dev()
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A D | g4x_dp.h | 20 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
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/linux-6.3-rc2/drivers/gpu/drm/gma500/ |
A D | psb_intel_display.c | 168 dpll |= in psb_intel_crtc_mode_set() 192 dpll |= 3; in psb_intel_crtc_mode_set() 220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set() 255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 256 REG_READ(map->dpll); in psb_intel_crtc_mode_set() 261 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 310 u32 dpll; in psb_intel_crtc_clock_get() local 317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get() 325 dpll = p->dpll; in psb_intel_crtc_clock_get() 342 ffs((dpll & in psb_intel_crtc_clock_get() [all …]
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A D | oaktrail_crtc.c | 251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms() 527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set() 530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 533 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set() 541 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set() 542 dpll |= in oaktrail_crtc_mode_set() 554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set() 559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set() 568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set() [all …]
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A D | cdv_intel_display.c | 665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set() 722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set() 723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set() 767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set() 769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 842 u32 dpll; in cdv_intel_crtc_clock_get() local 849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get() 857 dpll = p->dpll; in cdv_intel_crtc_clock_get() 873 ffs((dpll & in cdv_intel_crtc_clock_get() [all …]
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A D | gma_display.c | 223 temp = REG_READ(map->dpll); in gma_crtc_dpms() 225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms() 226 REG_READ(map->dpll); in gma_crtc_dpms() 230 REG_READ(map->dpll); in gma_crtc_dpms() 234 REG_READ(map->dpll); in gma_crtc_dpms() 311 temp = REG_READ(map->dpll); in gma_crtc_dpms() 314 REG_READ(map->dpll); in gma_crtc_dpms() 595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save() 634 REG_WRITE(map->dpll, in gma_crtc_restore() 636 REG_READ(map->dpll); in gma_crtc_restore() [all …]
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A D | oaktrail_hdmi.c | 285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local 295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set() 296 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set() 297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set() 311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set() 312 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set() 313 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set() 317 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
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A D | oaktrail_device.c | 144 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers() 261 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers() 402 .dpll = MRST_DPLL_A, 426 .dpll = DPLL_B,
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/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ti/ |
A D | dpll.txt | 18 "ti,omap3-dpll-clock", 19 "ti,omap3-dpll-core-clock", 20 "ti,omap3-dpll-per-clock", 22 "ti,omap4-dpll-clock", 23 "ti,omap4-dpll-x2-clock", 24 "ti,omap4-dpll-core-clock", 27 "ti,omap5-mpu-dpll-clock", 29 "ti,am3-dpll-j-type-clock", 31 "ti,am3-dpll-clock", 32 "ti,am3-dpll-core-clock", [all …]
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/linux-6.3-rc2/Documentation/devicetree/bindings/media/i2c/ |
A D | adv748x.yaml | 38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] [all …]
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/linux-6.3-rc2/arch/arm/boot/dts/ |
A D | dra7xx-clocks.dtsi | 235 dpll_abe_x2_ck: clock-dpll-abe-x2 { 305 dpll_core_x2_ck: clock-dpll-core-x2 { 382 compatible = "ti,omap4-dpll-clock"; 424 compatible = "ti,omap4-dpll-clock"; 466 compatible = "ti,omap4-dpll-clock"; 520 compatible = "ti,omap4-dpll-clock"; 549 compatible = "ti,omap4-dpll-clock"; 632 compatible = "ti,omap4-dpll-clock"; 719 dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 738 dpll_dsp_x2_ck: clock-dpll-dsp-x2 { [all …]
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A D | am43xx-clocks.dtsi | 231 compatible = "ti,am3-dpll-core-clock"; 237 dpll_core_x2_ck: clock-dpll-core-x2 { 239 compatible = "ti,am3-dpll-x2-clock"; 282 compatible = "ti,am3-dpll-clock"; 288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { 311 compatible = "ti,am3-dpll-clock"; 331 compatible = "ti,am3-dpll-clock"; 352 compatible = "ti,am3-dpll-j-type-clock"; 635 compatible = "ti,am3-dpll-clock"; 711 dpll_ddr_x2_ck: clock-dpll-ddr-x2 { [all …]
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A D | am33xx-clocks.dtsi | 190 compatible = "ti,am3-dpll-core-clock"; 196 dpll_core_x2_ck: clock-dpll-core-x2 { 198 compatible = "ti,am3-dpll-x2-clock"; 203 dpll_core_m4_ck: clock-dpll-core-m4@480 { 213 dpll_core_m5_ck: clock-dpll-core-m5@484 { 223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 { 235 compatible = "ti,am3-dpll-clock"; 241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { 259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { 286 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { [all …]
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A D | omap54xx-clocks.dtsi | 119 compatible = "ti,omap4-dpll-m4xen-clock"; 127 compatible = "ti,omap4-dpll-x2-clock"; 201 compatible = "ti,omap4-dpll-core-clock"; 209 compatible = "ti,omap4-dpll-x2-clock"; 352 compatible = "ti,omap4-dpll-clock"; 362 compatible = "ti,omap4-dpll-x2-clock"; 402 compatible = "ti,omap5-mpu-dpll-clock"; 586 compatible = "ti,omap4-dpll-clock"; 594 compatible = "ti,omap4-dpll-x2-clock"; 661 compatible = "ti,omap4-dpll-clock"; [all …]
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/linux-6.3-rc2/arch/arm/mach-omap1/ |
A D | sram.S | 36 strh r0, [r2] @ set dpll into bypass mode 41 strh r0, [r2] @ write new dpll value 49 lock: ldrh r4, [r2], #0 @ read back dpll value 52 tst r4, #1 << 0 @ dpll rate locked?
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/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ |
A D | microchip,sparx5-dpll.yaml | 4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# 18 const: microchip,sparx5-dpll 46 compatible = "microchip,sparx5-dpll";
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/linux-6.3-rc2/drivers/ata/ |
A D | pata_hpt3x2n.c | 312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local 319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer() 328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local 330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue() 332 flags |= dpll; in hpt3x2n_qc_issue() 335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
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A D | pata_hpt37x.c | 948 int dpll, adjust; in hpt37x_init_one() local 951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one() 953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one() 981 if (dpll == 3) in hpt37x_init_one() 987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
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/linux-6.3-rc2/drivers/gpu/drm/rcar-du/ |
A D | rcar_du_crtc.c | 83 struct dpll_info *dpll, in rcar_du_dpll_divider() argument 147 dpll->n = n; in rcar_du_dpll_divider() 148 dpll->m = m; in rcar_du_dpll_divider() 149 dpll->fdpll = fdpll; in rcar_du_dpll_divider() 150 dpll->output = output; in rcar_du_dpll_divider() 162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider() 217 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local 241 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing() 244 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing() 245 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
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/linux-6.3-rc2/drivers/video/fbdev/intelfb/ |
A D | intelfbhw.c | 688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2() 691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2() 697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2() 1043 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local 1058 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw() 1070 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw() 1131 *dpll &= ~DPLL_P1_FORCE_DIV2; in intelfbhw_mode_to_hw() 1136 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT); in intelfbhw_mode_to_hw() 1301 dpll = &hw->dpll_b; in intelfbhw_program_mode() 1325 dpll = &hw->dpll_a; in intelfbhw_program_mode() [all …]
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/linux-6.3-rc2/arch/arm64/boot/dts/sprd/ |
A D | sharkl3.dtsi | 123 dpll: dpll { label 124 compatible = "sprd,sc9863a-dpll";
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